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yosys/docs
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Charlotte 7f7c61c9f0 fmt: remove lzero by lowering during Verilog parse 
See https://github.com/YosysHQ/yosys/pull/3721#issuecomment-1502037466
-- this reduces logic within the cell, and makes the rules that apply
much more clear.
2023-08-11 04:46:52 +02:00
..
images
Remove docs dependency on yosys repo (#3558)
2022-11-24 15:56:44 +01:00
source
fmt: remove lzero by lowering during Verilog parse
2023-08-11 04:46:52 +02:00
static
Rst docs conversion (#3496)
2022-11-15 12:55:22 +01:00
util
Rst docs conversion (#3496)
2022-11-15 12:55:22 +01:00
.gitignore
Remove docs dependency on yosys repo (#3558)
2022-11-24 15:56:44 +01:00
Makefile
Rst docs conversion (#3496)
2022-11-15 12:55:22 +01:00