yosys/techlibs/quicklogic at 6f0e648543df970483b00dc73d9396d23f741bf4 - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00

Files

T

History

Emil J. Tywoniak 81fa4b1c5d techlibs: trivial twine damage

2026-10-02 18:42:01 +02:00

..

synth_quicklogic: rearrange files to prepare for adding more architectures

2023-12-04 15:52:02 +01:00

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

CMakeLists.txt

CMake: add missing dependency edges for synth_* passes.

2026-08-06 14:48:56 +00:00

ql_bram_merge.cc

techlibs: trivial twine damage

2026-10-02 18:42:01 +02:00

ql_bram_types.cc

techlibs: trivial twine damage

2026-10-02 18:42:01 +02:00

ql_dsp_io_regs.cc

techlibs: trivial twine damage

2026-10-02 18:42:01 +02:00

ql_dsp_macc.cc

techlibs: trivial twine damage

2026-10-02 18:42:01 +02:00

ql_dsp_macc.pmg

ql_dsp_macc: Tune DSP inference code

2023-12-04 15:52:02 +01:00

ql_dsp_simd.cc

techlibs: trivial twine damage

2026-10-02 18:42:01 +02:00

ql_ioff.cc

Remove .c_str() from parameters to log_debug()

2025-09-23 19:10:33 +12:00

synth_quicklogic.cc

Merge remote-tracking branch 'origin/main' into nella/latch-diagnostics-2

2026-09-22 16:49:41 +02:00