Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-07 18:43:22 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
66b2fdc8e4246a9f4f7aaa2c2dd8db01fc4d2942
yosys/passes
T
History
Emil J. Tywoniak df2ea7d788 memory: declare blackbox ports for generated RAM cells
2026-09-18 17:29:46 +02:00
..
cmds
passes: leave signorm mode where the index cannot be maintained
2026-09-18 17:29:46 +02:00
equiv
equiv_miter: don't copy $input_port
2026-09-17 15:43:54 +02:00
fsm
passes: leave signorm mode where the index cannot be maintained
2026-09-18 17:29:46 +02:00
hierarchy
passes: leave signorm mode where the index cannot be maintained
2026-09-18 17:29:46 +02:00
memory
memory: declare blackbox ports for generated RAM cells
2026-09-18 17:29:46 +02:00
opt
opt_clean: rewrite with signorm
2026-09-18 17:29:41 +02:00
pmgen
pmgen: hold sigmap pointer instead of owning it
2026-09-17 15:43:54 +02:00
proc
Merge branch 'main' into nella/latch-toggle
2026-07-08 11:41:08 +02:00
sat
signorm: disable passes that use rewrite_sigspecs
2026-09-17 14:13:57 +02:00
techmap
passes: leave signorm mode where the index cannot be maintained
2026-09-18 17:29:46 +02:00
tests
End of file fix
2026-06-23 07:23:41 +02:00
CMakeLists.txt
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
Powered by Gitea Version: 1.27.2 Page: 123ms Template: 3ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API