yosys/techlibs/quicklogic at 667004e9dcff6cf67bb6a5b1004fc681f58b9c72 - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 18:13:40 +02:00

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History

Miodrag Milanovic 667004e9dc Register rest of targets

2026-09-30 13:01:55 +02:00

..

synth_quicklogic: rearrange files to prepare for adding more architectures

2023-12-04 15:52:02 +01:00

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

CMakeLists.txt

CMake: add missing dependency edges for synth_* passes.

2026-08-06 14:48:56 +00:00

ql_bram_merge.cc

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

ql_bram_types.cc

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

ql_dsp_io_regs.cc

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

ql_dsp_macc.cc

Fixing couple more conversion errors

2026-05-14 15:58:58 +02:00

ql_dsp_macc.pmg

ql_dsp_macc: Tune DSP inference code

2023-12-04 15:52:02 +01:00

ql_dsp_simd.cc

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

ql_ioff.cc

Remove .c_str() from parameters to log_debug()

2025-09-23 19:10:33 +12:00

synth_quicklogic.cc

Register rest of targets

2026-09-30 13:01:55 +02:00