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luke
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yosys
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https://github.com/YosysHQ/yosys.git
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2026-10-06 18:13:40 +02:00
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667004e9dcff6cf67bb6a5b1004fc681f58b9c72
yosys
/
techlibs
/
intel
T
History
Miodrag Milanovic
667004e9dc
Register rest of targets
2026-09-30 13:01:55 +02:00
..
common
End of file fix
2026-06-23 07:23:41 +02:00
cyclone10lp
End of file fix
2026-06-23 07:23:41 +02:00
cycloneiv
End of file fix
2026-06-23 07:23:41 +02:00
cycloneive
End of file fix
2026-06-23 07:23:41 +02:00
max10
End of file fix
2026-06-23 07:23:41 +02:00
CMakeLists.txt
CMake: add missing dependency edges for
synth_*
passes.
2026-08-06 14:48:56 +00:00
synth_intel.cc
Register rest of targets
2026-09-30 13:01:55 +02:00