Emil J. Tywoniak 5f4be8c0a8 gowin: wire output clock enable ports to enable inputs, not constants		2026-03-11 20:38:52 +01:00
..
Makefile.inc	gowin: synth_gowin: Add MULT inference for GW1N and GW2A	2026-01-25 22:10:08 +03:00
adc.v	Gowin. Fix GW5A ADCs.	2025-10-29 12:48:21 +10:00
arith_map.v	gowin: Fix X output of $alu techmap	2023-05-01 17:56:41 +02:00
brams.txt	GOWIN. Disable read-before-write mode.	2026-03-05 09:17:37 +10:00
brams_map.v	gowin: wire output clock enable ports to enable inputs, not constants	2026-03-11 20:38:52 +01:00
brams_map_gw5a.v	gowin: Fix bram ADA byte enables	2026-02-22 09:00:37 +01:00
cells_map.v	iopadmap: Add native support for negative-polarity output enable.	2021-11-09 15:40:16 +01:00
cells_sim.v	Gowin. Renaming inputs of the DCS primitive.	2025-09-20 16:22:23 +01:00
cells_xtra.py	Gowin. Fix GW5A ADCs.	2025-10-29 12:48:21 +10:00
cells_xtra_gw1n.v	Add and use fix_mod.py	2026-01-28 07:45:58 +13:00
cells_xtra_gw2a.v	Add and use fix_mod.py	2026-01-28 07:45:58 +13:00
cells_xtra_gw5a.v	Add and use fix_mod.py	2026-01-28 07:45:58 +13:00
dsp_map.v	gowin: format MULT instances	2026-02-12 13:35:49 +03:00
lutrams.txt	gowin: Use `memory_libmap` pass.	2022-05-18 17:32:56 +02:00
lutrams_map.v	gowin: Use `memory_libmap` pass.	2022-05-18 17:32:56 +02:00
synth_gowin.cc	gowin: remove spurious warning	2026-02-27 13:12:32 +01:00