Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-01 18:47:29 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
58367cd87a5d2bac1de81512f60939c080b3b9ef
yosys/techlibs/common
T
History
Clifford Wolf a92a68ce52 Using "via_celltype" in $mul carry-save-acc implementation
2014-08-18 14:30:20 +02:00
..
adff2dff.v
Added adff2dff.v (for techmap -share_map)
2014-08-07 16:14:38 +02:00
blackbox.sed
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
Makefile.inc
Added adff2dff.v (for techmap -share_map)
2014-08-07 16:14:38 +02:00
pmux2mux.v
Added techlibs/common/pmux2mux.v
2014-01-17 20:06:15 +01:00
simcells.v
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
2014-08-16 18:29:39 +02:00
simlib.v
Renamed $lut ports to follow A-Y naming scheme
2014-08-15 14:18:40 +02:00
techmap.v
Using "via_celltype" in $mul carry-save-acc implementation
2014-08-18 14:30:20 +02:00
Powered by Gitea Version: 1.27.2 Page: 1498ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API