yosys/frontends/verilog
Emil J. Tywoniak 7713b5a811 verilog: fix case location 2026-01-26 12:50:51 +01:00
..
.gitignore
Makefile.inc
const2ast.cc
preproc.cc reduce OS ifdefs, refactor getting dirs and filenames from paths to files 2025-10-14 15:46:17 +02:00
preproc.h
verilog_error.cc
verilog_error.h
verilog_frontend.cc read_verilog: remove log I left behind by accident 2026-01-13 18:47:23 +01:00
verilog_frontend.h
verilog_lexer.h
verilog_lexer.l
verilog_location.h
verilog_parser.y verilog: fix case location 2026-01-26 12:50:51 +01:00