..
dynamic_part_select
Add torture test for (* nowrshmsk *) stride optimization
2024-01-10 20:28:36 +01:00
.gitignore
Ignore some generated files
2026-04-16 11:00:44 +02:00
abc9.v
Another sloppy mistake!
2019-11-21 16:33:20 -08:00
abc9.ys
abc9: uniquify blackboxes like whiteboxes ( #2695 )
2021-03-29 22:02:06 -07:00
abstract_init.ys
abstract: test -slice from:to for -init
2025-02-25 00:22:14 +01:00
abstract_initstates.ys
abstract: Add -initstates option
2025-08-12 15:37:12 +02:00
abstract_state.ys
abstract: test -slice for all modes, -rtlilslice for -init
2025-02-25 00:18:16 +01:00
abstract_value.ys
abstract: test -slice for all modes, -rtlilslice for -init
2025-02-25 00:18:16 +01:00
aiger2.ys
kernel: Rewrite bufNormalize
2025-09-17 13:56:46 +02:00
aiger_dff.ys
write_aiger: Fix non-$_FF_ FFs
2022-08-18 13:56:22 +02:00
async.sh
Make out of tree build testing possible
2026-05-19 14:26:07 +02:00
async.v
Fix tests/various/async FFL test
2019-07-09 22:44:39 +02:00
attrib05_port_conn.v
Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
2019-06-04 10:42:42 +02:00
attrib05_port_conn.ys
Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
2019-06-04 10:42:42 +02:00
attrib07_func_call.v
tests: fix some test warnings
2020-05-25 10:07:58 -07:00
attrib07_func_call.ys
Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
2019-06-04 10:42:42 +02:00
autoname.ys
autoname.ys: Extra check for rename order
2025-09-26 11:36:23 +12:00
blackbox_wb.ys
blackbox: Include whiteboxed modules
2021-03-17 13:58:04 +00:00
box_derive.ys
box_derive: rename -apply to -apply_derived_type
2025-10-13 17:24:32 +02:00
bufnorm_opt_clean.ys
bufnorm: Refactor and fix incremental bufNormalize
2025-09-29 08:21:28 +02:00
bug1496.ys
Remove references to ilang
2024-11-05 12:36:31 +13:00
bug1531.ys
Add testcase
2019-12-11 16:52:37 -08:00
bug1614.ys
add testcase for #1614
2020-02-03 21:29:54 +01:00
bug1710.ys
ast: fixes #1710 ; do not generate RTLIL for unreachable ternary
2020-02-27 16:55:55 -08:00
bug1745.ys
Add regression tests for new handling of comments in constants
2020-03-14 11:41:09 +01:00
bug1781.ys
fsm_extract: Initialize celltypes with full design.
2020-03-19 18:51:21 +01:00
bug1876.ys
tests: add testcases from #1876
2020-04-14 12:39:10 -07:00
bug2014.ys
test: add test for #2014
2020-05-02 14:22:37 -07:00
bug3462.ys
Add test for bug 3462
2022-08-29 10:10:09 +02:00
bug3515.v
tests: Add bug3515
2025-11-25 07:04:34 +13:00
bug3515.ys
tests: Tidy up bug3515
2025-11-25 07:35:19 +13:00
bug3879.ys
extract_fa: Add test case
2025-01-30 18:45:06 +01:00
bug4082.ys
rtlil: Add wire deletion test
2024-01-29 11:25:54 +01:00
bug4865.ys
ice40_dsp: fix test
2025-03-26 15:13:05 +02:00
bug4909.ys
splitcells: add tests
2025-03-10 19:41:22 +02:00
cellarray_array_connections.ys
simplify: regression test for AST_CELLARRAY simplification issue
2022-12-07 18:41:55 +01:00
celledges_shift.ys
celledges: Add test of shift cells edge data
2024-01-19 11:14:10 +01:00
check.ys
check: Extend testing
2024-03-11 10:45:17 +01:00
check_2.ys
check: Extend testing
2024-03-11 10:45:17 +01:00
check_3.ys
check: Rephrase regex for portability
2024-03-11 10:45:17 +01:00
check_4.ys
celledges: Add read ports arst paths
2024-03-11 10:45:17 +01:00
chformal_check.ys
chformal: Add -assert2cover option
2025-06-14 10:54:23 +12:00
chformal_coverenable.ys
Additional tests for FV $check compatibility
2024-02-02 16:07:10 +01:00
chparam.sh
Make out of tree build testing possible
2026-05-19 14:26:07 +02:00
clk2fflogic_effects.sh
Make out of tree build testing possible
2026-05-19 14:26:07 +02:00
clk2fflogic_effects.sv
clk2fflogic: Fix handling of $check cells
2024-02-14 11:42:27 +01:00
const_arg_loop.sv
verilog: fix sizing of constant args for tasks/functions
2021-02-21 15:44:43 -05:00
const_arg_loop.ys
tests: remove -seq 1 from sat with -tempinduct where possible
2025-09-08 18:04:32 +02:00
const_func.sv
verilog: fix sizing of constant args for tasks/functions
2021-02-21 15:44:43 -05:00
const_func.ys
tests: remove -seq 1 from sat with -tempinduct where possible
2025-09-08 18:04:32 +02:00
const_func_block_var.v
Allow localparams in constant functions
2020-08-20 20:10:24 -04:00
const_func_block_var.ys
Allow blocks with declarations within constant functions
2020-07-25 10:16:12 -06:00
const_shift_empty_arg.ys
Fix segfault from shift with 0-width signed arg.
2026-02-12 22:03:42 -06:00
constant_drive_conflict.ys
check: Also check for conflicts with constant drivers
2023-06-23 18:07:28 +02:00
constcomment.ys
Add regression tests for new handling of comments in constants
2020-03-14 11:41:09 +01:00
constmsk_test.v
Added tests/various/constmsk_test.ys
2014-09-04 15:07:30 +02:00
constmsk_test.ys
Added tests/various/constmsk_test.ys
2014-09-04 15:07:30 +02:00
constmsk_testmap.v
tests: fix some test warnings
2020-05-25 10:07:58 -07:00
countbits.sv
Add tests for $countbits
2021-02-26 12:28:58 -05:00
countbits.ys
tests: remove -seq 1 from sat with -tempinduct where possible
2025-09-08 18:04:32 +02:00
cutpoint_blackbox.ys
cutpoint_blackbox.ys: Extra edge case
2025-08-06 18:11:35 +12:00
cutpoint_whole.ys
cutpoint: Re-add whole module optimization
2025-05-06 09:57:34 +12:00
debugon.ys
Add -on/-off modes to debug pass
2026-01-15 12:07:26 -08:00
deminout_unused.ys
deminout: Don't demote inouts with unused bits
2020-03-04 18:44:38 +00:00
design.ys
design: add test
2020-04-16 12:48:40 -07:00
design1.ys
design: add test
2020-04-16 12:48:40 -07:00
design2.ys
tests: add design -delete tests
2020-04-16 08:05:18 -07:00
design_equal_fail.ys
Implement design_equal command
2025-12-21 21:47:40 +00:00
design_equal_pass.ys
Implement design_equal command
2025-12-21 21:47:40 +00:00
dynamic_part_select.ys
Add torture test for (* nowrshmsk *) stride optimization
2024-01-10 20:28:36 +01:00
elab_sys_tasks.sv
Initial implementation of elaboration system tasks
2019-05-03 03:10:43 +03:00
elab_sys_tasks.ys
Initial implementation of elaboration system tasks
2019-05-03 03:10:43 +03:00
equiv_assume.ys
tests: Add equiv_induct to equiv_assume.ys
2025-08-06 15:13:04 +12:00
equiv_make_make_assert.ys
equiv_make: Add -make_assert option
2022-06-24 00:17:02 +01:00
equiv_opt_multiclock.ys
Add equiv_opt -multiclock
2019-09-11 13:55:59 +01:00
equiv_opt_undef.ys
Remove references to ilang
2024-11-05 12:36:31 +13:00
exec.ys
Add test for `exec` command.
2020-03-16 07:52:58 +00:00
ezcmdline_dummy_solver
Remove FHS dependency by replacing /bin/sh with /usr/bin/env sh
2026-04-23 15:55:11 +02:00
ezcmdline_plugin.cc
Add test for ezCmdlineSAT
2026-01-20 09:28:00 -08:00
ezcmdline_plugin.sh
Make out of tree build testing possible
2026-05-19 14:26:07 +02:00
fib.v
verilog: improved support for recursive functions
2020-12-31 18:33:59 -07:00
fib.ys
verilog: improved support for recursive functions
2020-12-31 18:33:59 -07:00
fib_tern.v
verilog: support recursive functions using ternary expressions
2021-02-12 14:43:42 -05:00
fib_tern.ys
verilog: support recursive functions using ternary expressions
2021-02-12 14:43:42 -05:00
formalff_declockgate.ys
formalff: Fix -declockgate test and missing emit for memories
2025-04-18 18:57:59 +02:00
fsm-arst.ys
typo
2025-11-14 13:34:58 +02:00
func_port_implied_dir.sv
sv: complete support for implied task/function port directions
2020-12-31 16:17:13 -07:00
func_port_implied_dir.ys
sv: complete support for implied task/function port directions
2020-12-31 16:17:13 -07:00
gen_if_null.v
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
gen_if_null.ys
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
generate_mk.py
Convert gen-tests shell script to python
2026-04-16 11:00:44 +02:00
global_scope.ys
ast: Fix handling of identifiers in the global scope
2020-04-16 10:30:07 +01:00
gzip_verilog.v.gz
Add support for reading gzip'd input files
2019-07-26 10:23:58 +01:00
gzip_verilog.ys
Add support for reading gzip'd input files
2019-07-26 10:23:58 +01:00
help.ys
tests: Fix invocation of 'help -cells'
2023-07-10 12:42:09 +02:00
hierarchy.sh
Make out of tree build testing possible
2026-05-19 14:26:07 +02:00
hierarchy_defer.ys
Expand test with `hierarchy' without -auto-top
2019-09-03 12:17:26 -07:00
hierarchy_generate.ys
add command that should not have any effect to hierarchy -generate test (this documents the current behavior, not sure if it is desired functionality)
2024-04-12 13:51:06 +02:00
hierarchy_param.ys
hierarchy: Convert positional parameters to named.
2020-04-21 19:09:00 +02:00
ice40_mince_abc9.ys
Add test for abc9+mince issue
2020-03-20 20:35:28 +00:00
integer_range_bad_syntax.ys
Revert "Revert PRs #2203 and #2244."
2020-07-10 09:59:48 +02:00
integer_real_bad_syntax.ys
Revert "Revert PRs #2203 and #2244."
2020-07-10 09:59:48 +02:00
json_escape_chars.ys
fix handling of escaped chars in json backend and frontend
2022-02-18 17:13:09 +01:00
json_param_defaults.v
Add tests
2026-02-11 08:10:57 -08:00
json_param_defaults.ys
Don't dump params by default
2026-02-11 08:33:39 -08:00
json_scopeinfo.ys
emit $scopeinfo cells by default
2025-01-08 14:47:46 +01:00
keep_hierarchy.ys
Add keep_hierarchy test
2024-11-05 09:28:45 +01:00
lcov.gold
print summary of line coverage to log
2025-07-16 13:40:07 +02:00
lcov.v
update test to use suggested selection for assertions
2025-07-01 11:46:27 +02:00
lcov.ys
update test to use suggested selection for assertions
2025-07-01 11:46:27 +02:00
logger_cmd_error.sh
Make out of tree build testing possible
2026-05-19 14:26:07 +02:00
logger_error.ys
Added back tests for logger
2020-03-13 15:00:18 +01:00
logger_fail.sh
Make out of tree build testing possible
2026-05-19 14:26:07 +02:00
logger_nowarning.ys
Added back tests for logger
2020-03-13 15:00:18 +01:00
logger_warn.ys
Added back tests for logger
2020-03-13 15:00:18 +01:00
logger_warning.ys
Added back tests for logger
2020-03-13 15:00:18 +01:00
logic_param_simple.ys
Revert "Revert PRs #2203 and #2244."
2020-07-10 09:59:48 +02:00
mem2reg.ys
Change attribute search value to specify precise location instead of simple line number.
2020-02-24 01:39:36 +00:00
memory_word_as_index.data
Fix elaboration of whole memory words used as indices
2020-12-26 21:47:38 -07:00
memory_word_as_index.v
Fix elaboration of whole memory words used as indices
2020-12-26 21:47:38 -07:00
memory_word_as_index.ys
Fix elaboration of whole memory words used as indices
2020-12-26 21:47:38 -07:00
muxcover.ys
muxcover: do not add decode muxes with x inputs
2023-01-26 05:19:45 +00:00
muxpack.v
More deadname stuff
2021-06-09 12:40:33 +02:00
muxpack.ys
More deadname stuff
2021-06-09 12:40:33 +02:00
muxpack_wide_y.ys
Regression test for #5765
2026-03-30 08:59:28 -07:00
param_struct.ys
tests: remove -seq 1 from sat with -tempinduct where possible
2025-09-08 18:04:32 +02:00
peepopt.ys
peepopt: Fix padding for the peepopt_shiftmul_right pattern
2023-12-06 18:35:44 +01:00
peepopt_formal.ys
peepopt clockgateff: add testcase
2024-08-07 10:21:52 +01:00
plugin.cc
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
plugin.sh
Make out of tree build testing possible
2026-05-19 14:26:07 +02:00
pmgen_reduce.ys
Add test for pmtest_test "reduce" demo pattern
2019-08-17 14:05:10 +02:00
pmux2shiftx.v
Cleanup tests
2020-02-27 10:17:29 -08:00
pmux2shiftx.ys
Add #1135 testcase
2019-06-27 11:02:52 -07:00
port_sign_extend.v
genrtlil: fix signed port connection codegen failures
2021-02-05 19:51:30 -05:00
port_sign_extend.ys
genrtlil: fix signed port connection codegen failures
2021-02-05 19:51:30 -05:00
primitives.ys
tests: add tests for primitives' src
2020-05-04 10:21:47 -07:00
printattr.ys
printattrs: Add test.
2020-05-27 08:00:00 +00:00
rand_const.sv
Allow combination of rand and const modifiers
2021-01-21 08:42:05 -07:00
rand_const.ys
Allow combination of rand and const modifiers
2021-01-21 08:42:05 -07:00
reg_wire_error.sv
Modified errors into warnings
2018-06-05 18:03:22 +03:00
reg_wire_error.ys
reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files
2018-06-05 18:00:06 +03:00
rename_scramble_name.ys
rename: add -scramble-name option to randomly rename selections
2022-08-08 16:03:28 +01:00
rename_unescape.ys
rename.cc: Fixup ports after -unescape
2025-08-15 10:48:32 +12:00
rename_wire_move_to_cell.ys
rename: add -move-to-cell option in -wire mode
2025-08-13 11:11:52 +02:00
rtlil_signed_attribute.ys
Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting
2024-08-21 14:28:42 +01:00
rtlil_z_bits.ys
backends/rtlil: Do not shorten a value with z bits to 'x
2023-01-29 14:02:25 +01:00
scopeinfo.ys
Test flatten and opt_clean's $scopeinfo handling
2024-02-06 17:51:29 +01:00
scratchpad.ys
add assert option to scratchpad command
2019-12-16 14:00:21 +01:00
script.ys
Update test for Pass::call_on_module()
2019-07-02 08:22:31 -07:00
setundef.sv
Fix setting bits of parameters in setundef pass
2024-11-08 17:03:08 +01:00
setundef.ys
Fix setting bits of parameters in setundef pass
2024-11-08 17:03:08 +01:00
setundef_init.ys
setundef: strip init attributes from undriven wires ( fixes #5835 )
2026-05-31 00:18:49 +08:00
setundef_selection.ys
changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change
2026-03-08 20:14:03 -04:00
setundef_selection_ff.il
setundef: add tests for selection in -zero, -undriven, and -init modes. also made setundef.cc clearer
2026-03-06 18:12:03 -05:00
setundef_selection_undriven.v
changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change
2026-03-08 20:14:03 -04:00
sformatf.ys
ast: use new format string helpers.
2023-08-11 04:46:52 +02:00
shregmap.v
tests: fix some test warnings
2020-05-25 10:07:58 -07:00
shregmap.ys
Remove Xilinx test
2019-08-22 16:18:07 -07:00
signed.ys
Revert "Revert PRs #2203 and #2244."
2020-07-10 09:59:48 +02:00
signext.ys
Extend sign extension tests
2019-06-20 12:43:59 -07:00
sim_const.ys
sim: Fix handling of constant-connected cell inputs at startup
2020-04-21 08:58:52 +01:00
specify.v
verilog: ignore ranges too without -specify
2020-02-13 17:58:43 -08:00
specify.ys
specify: fix test
2026-02-03 18:40:32 +01:00
splitnets.ys
splitnets: handle single-bit vectors consistently
2025-06-05 10:58:06 +02:00
src.ys
verilog: add test
2020-03-11 06:51:03 -07:00
sta.ys
sta: very crude static timing analysis pass
2021-11-25 17:20:27 +01:00
stat.ys
updated testcase
2025-08-16 09:32:08 +02:00
stat_area_by_width.lib
removed copyright notice on lib file.
2025-08-16 09:40:03 +02:00
stat_hierarchy.ys
add Testcases
2025-08-13 14:46:01 +02:00
stat_high_level.ys
testcases
2025-08-16 09:40:03 +02:00
stat_high_level2.ys
testcases
2025-08-16 09:40:03 +02:00
struct_access.sv
Fix access to whole sub-structs ( #3086 )
2022-02-14 14:34:20 +01:00
struct_access.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
sub.v
Add test for bug 3462
2022-08-29 10:10:09 +02:00
submod.ys
Remove submod changes
2019-12-30 14:56:14 -08:00
submod_extract.ys
Added tests/various/submod_extract.ys
2014-07-26 17:22:18 +02:00
sv_defines.ys
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-27 16:08:26 +00:00
sv_defines_dup.ys
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-27 16:08:26 +00:00
sv_defines_mismatch.ys
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-27 16:08:26 +00:00
sv_defines_too_few.ys
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-27 16:08:26 +00:00
sv_implicit_ports.sh
Make out of tree build testing possible
2026-05-19 14:26:07 +02:00
svalways.sh
proc: ignore nosync temporaries in always_latch checks
2026-05-26 00:56:07 +08:00
tcl_apis.tcl
Redo integer passing on top of bignum
2024-12-02 19:56:51 +01:00
tcl_apis.v
Redo integer passing on top of bignum
2024-12-02 19:56:51 +01:00
tcl_apis.ys
Fix test
2024-11-04 16:19:59 +01:00
timeest.ys
timeest: Add top ports launching/sampling
2025-11-03 14:21:28 +01:00
wrapcell.ys
wrapcell: Test `check -assert` post wrapping
2024-12-10 15:13:31 +01:00
wreduce.ys
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
2019-08-12 12:06:45 -07:00
wreduce2.ys
wreduce: Optimize signedness when possible
2024-12-16 12:57:08 +01:00
write_gzip.ys
Do not use Verific in tests/various/write_gzip.ys
2019-08-16 14:22:46 +02:00
xaiger.ys
xaiger: add testcase
2020-05-24 08:48:23 -07:00
46f9f887f7