xaiger: add testcase

2026-10-06 01:53:53 +02:00 · 2020-05-24 08:48:23 -07:00
parent d64df21630
commit 33b03ce904
1 changed files with 13 additions and 0 deletions
@@ -0,0 +1,13 @@
+read_verilog <<EOT
+module top(input a, b, output c);
+bb #(1) bb();
+endmodule
+
+module bb(input a, b, output c);
+parameter p = 0;
+assign c = a ^ b;
+endmodule
+EOT
+blackbox bb
+hierarchy
+write_xaiger /dev/null