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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 01:53:53 +02:00
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440778f2283d1f69bacbf6697a2017c46c8d1217
yosys/frontends
T
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Miodrag Milanovic 440778f228 verific: make use of target register
2026-09-30 10:54:07 +02:00
..
aiger
Revert "Temporarily revert #6101 and #6077"
2026-09-10 09:09:13 +02:00
ast
read_verilog logging to_src() - > to_loc()
2026-09-16 12:30:40 +02:00
blif
abc: re-isolate autoidx churn
2026-09-10 18:16:57 +02:00
json
json: read 'signed' attribute on netnames, matching ports
2026-08-20 22:20:24 -07:00
liberty
Don't mark cells w no unput as boxes.
2026-09-21 16:58:03 +02:00
rpc
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
rtlil
long long to int truncation checks
2026-07-10 14:36:39 +02:00
slang
Update sv-elab and slang to v12.0
2026-09-29 18:09:25 +02:00
verific
verific: make use of target register
2026-09-30 10:54:07 +02:00
verilog
read_verilog logging to_src() - > to_loc()
2026-09-16 12:30:40 +02:00
CMakeLists.txt
Revert "Temporarily revert #6101 and #6077"
2026-09-10 09:09:13 +02:00
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