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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00
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40c50f62550deadc337194c2f5466a3368ab32ff
yosys/frontends
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nella 315f8194a0 Don't mark cells w no unput as boxes.
2026-09-21 16:58:03 +02:00
..
aiger
Revert "Temporarily revert #6101 and #6077"
2026-09-10 09:09:13 +02:00
ast
Merge pull request #6161 from YosysHQ/emil/remove-dead-bindings
2026-09-09 16:51:35 +00:00
blif
abc: re-isolate autoidx churn
2026-09-10 18:16:57 +02:00
json
json: read 'signed' attribute on netnames, matching ports
2026-08-20 22:20:24 -07:00
liberty
Don't mark cells w no unput as boxes.
2026-09-21 16:58:03 +02:00
rpc
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
rtlil
long long to int truncation checks
2026-07-10 14:36:39 +02:00
slang
sv-elab: Update to release 2026-09-08
2026-09-08 11:58:13 +02:00
verific
Fix remaining mentions, and update links
2026-09-10 10:24:34 +02:00
verilog
rtlil: remove dead verilog bindings
2026-08-31 22:13:01 +02:00
CMakeLists.txt
Revert "Temporarily revert #6101 and #6077"
2026-09-10 09:09:13 +02:00
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