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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 19:19:48 +02:00
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3ccdab940cd054d996a5ce94010918edd782cae0
yosys/techlibs/intel/max10
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Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes.
Fixes #2058.
2020-05-19 01:42:40 +02:00
..
cells_arith.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
cells_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
cells_sim.v
Clean whitespace and permissions in techlibs/intel
2017-10-05 16:23:49 +02:00
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