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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-01 10:39:10 +02:00
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3ccdab940cd054d996a5ce94010918edd782cae0
yosys/techlibs/intel
T
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whitequark 7191dd16f9 Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
..
arria10gx
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
common
intel: Map M9K BRAM only on families that have it
2019-07-23 18:11:11 +01:00
cyclone10lp
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
cycloneiv
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
cycloneive
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
cyclonev
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
max10
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
Makefile.inc
synth_intel_alm: alternative synthesis for Intel FPGAs
2020-04-15 11:40:41 +02:00
synth_intel.cc
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
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