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Dan Ravensloft 5b779f7f4e intel_alm: direct LUTRAM cell instantiation 
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.

While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
2020-05-07 21:03:13 +02:00
..
alm_map.v
synth_intel_alm: alternative synthesis for Intel FPGAs
2020-04-15 11:40:41 +02:00
alm_sim.v
intel_alm: Documentation improvements
2020-04-21 19:38:15 +02:00
arith_alm_map.v
synth_intel_alm: alternative synthesis for Intel FPGAs
2020-04-15 11:40:41 +02:00
bram_m10k_map.v
intel_alm: direct LUTRAM cell instantiation
2020-05-07 21:03:13 +02:00
bram_m10k.txt
synth_intel_alm: alternative synthesis for Intel FPGAs
2020-04-15 11:40:41 +02:00
bram_m20k_map.v
synth_intel_alm: alternative synthesis for Intel FPGAs
2020-04-15 11:40:41 +02:00
bram_m20k.txt
synth_intel_alm: alternative synthesis for Intel FPGAs
2020-04-15 11:40:41 +02:00
dff_map.v
intel_alm: Documentation improvements
2020-04-21 19:38:15 +02:00
dff_sim.v
intel_alm: Documentation improvements
2020-04-21 19:38:15 +02:00
lutram_mlab.txt
intel_alm: direct LUTRAM cell instantiation
2020-05-07 21:03:13 +02:00
megafunction_bb.v
intel_alm: direct LUTRAM cell instantiation
2020-05-07 21:03:13 +02:00
mem_sim.v
intel_alm: direct LUTRAM cell instantiation
2020-05-07 21:03:13 +02:00
quartus_rename.v
intel_alm: direct LUTRAM cell instantiation
2020-05-07 21:03:13 +02:00