mirror of https://github.com/YosysHQ/yosys.git
97 lines
1.7 KiB
Verilog
97 lines
1.7 KiB
Verilog
module \$__MUL27X18 (input [26:0] A, input [17:0] B, output [44:0] Y);
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parameter A_WIDTH = 27;
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parameter B_WIDTH = 18;
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parameter Y_WIDTH = 45;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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wire [47:0] dout_w;
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MULTALU27X18 #(
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.MULT12X12_EN("FALSE"),
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.MULT_RESET_MODE("SYNC"),
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.C_SEL(1'b0),
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.AREG_CLK("BYPASS"),
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.BREG_CLK("BYPASS"),
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.PREG_CLK("BYPASS"),
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.OREG_CLK("BYPASS")
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) __TECHMAP_REPLACE__ (
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.DOUT(dout_w),
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.CASO(),
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.SOA(),
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.A(A),
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.SIA(27'd0),
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.B(B),
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.C(48'd0),
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.D(26'd0),
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.CASI(48'd0),
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.ACCSEL(1'b0),
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.PSEL(1'b0),
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.ASEL(1'b0),
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.PADDSUB(1'b0),
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.CSEL(1'b0),
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.CASISEL(1'b0),
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.ADDSUB(2'b00),
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.CLK(2'b00),
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.CE(2'b00),
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.RESET(2'b00)
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);
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assign Y = dout_w[44:0];
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endmodule
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module \$__MUL12X12 (input [11:0] A, input [11:0] B, output [23:0] Y);
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parameter A_WIDTH = 12;
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parameter B_WIDTH = 12;
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parameter Y_WIDTH = 24;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT12X12 #(
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.MULT_RESET_MODE("SYNC"),
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.AREG_CLK("BYPASS"),
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.BREG_CLK("BYPASS"),
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.PREG_CLK("BYPASS"),
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.OREG_CLK("BYPASS")
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) __TECHMAP_REPLACE__ (
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.DOUT(Y),
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.A(A),
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.B(B),
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.CLK(2'b00),
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.CE(2'b00),
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.RESET(2'b00)
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);
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endmodule
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module \$__MUL27X36 (input [26:0] A, input [35:0] B, output [62:0] Y);
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parameter A_WIDTH = 27;
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parameter B_WIDTH = 36;
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parameter Y_WIDTH = 63;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT27X36 #(
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.MULT_RESET_MODE("SYNC"),
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.AREG_CLK("BYPASS"),
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.BREG_CLK("BYPASS"),
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.PREG_CLK("BYPASS"),
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.OREG_CLK("BYPASS")
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) __TECHMAP_REPLACE__ (
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.DOUT(Y),
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.A(A),
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.B(B),
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.D(26'd0),
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.PSEL(1'b0),
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.PADDSUB(1'b0),
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.CLK(2'b00),
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.CE(2'b00),
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.RESET(2'b00)
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);
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endmodule
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