yosys/techlibs
Johan Olby 3540d700a3
gowin: Correct B_MINWIDTH for 27x17
The 27x18 rule carried B_MINWIDTH=13, so any product whose narrower operand
was below 13 (e.g. 27x4, 4x13) was rejected even though it fits one
MULTALU27X18 tile, and decomposed onto MULT12X12 partials instead. Drop the
floor to 2 so the rule blocks only degenerate Nx1 multiplies, matching the
rest of the tree.

Adds a 4x13 regression case.
2026-07-16 17:35:55 +02:00
..
achronix End of file fix 2026-06-23 07:23:41 +02:00
analogdevices Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
anlogic Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
common mul2dsp: normalize operand order 2026-07-15 16:21:07 +02:00
coolrunner2 Migrate build system to CMake 2026-06-03 08:58:10 +00:00
easic Migrate build system to CMake 2026-06-03 08:58:10 +00:00
efinix Merge branch 'main' into nella/latch-toggle 2026-07-08 11:41:08 +02:00
fabulous Remove old techmap. 2026-07-08 12:07:58 +02:00
gatemate Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
gowin gowin: Correct B_MINWIDTH for 27x17 2026-07-16 17:35:55 +02:00
greenpak4 Migrate build system to CMake 2026-06-03 08:58:10 +00:00
ice40 Merge branch 'main' into nella/latch-toggle 2026-07-08 11:41:08 +02:00
intel End of file fix 2026-06-23 07:23:41 +02:00
intel_alm Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
lattice Merge branch 'main' into nella/latch-toggle 2026-07-08 11:41:08 +02:00
microchip Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
nanoxplore Merge branch 'main' into nella/latch-toggle 2026-07-08 11:41:08 +02:00
quicklogic Merge branch 'main' into nella/latch-toggle 2026-07-08 11:41:08 +02:00
sf2 Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
xilinx Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
CMakeLists.txt Migrate build system to CMake 2026-06-03 08:58:10 +00:00
fix_mod.py Remove trailing whitespaces 2026-06-23 07:24:59 +02:00