luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

gowin: Correct B_MINWIDTH for 27x17 

The 27x18 rule carried B_MINWIDTH=13, so any product whose narrower operand
was below 13 (e.g. 27x4, 4x13) was rejected even though it fits one
MULTALU27X18 tile, and decomposed onto MULT12X12 partials instead. Drop the
floor to 2 so the rule blocks only degenerate Nx1 multiplies, matching the
rest of the tree.

Adds a 4x13 regression case.
This commit is contained in:
Johan Olby 2026-07-16 17:35:55 +02:00
parent e54c4fc737
commit 3540d700a3
No known key found for this signature in database
GPG Key ID: 099308365347DFA9
2 changed files with 14 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
techlibs/gowin/synth_gowin.cc
View File

@ -46,7 +46,7 @@ struct SynthGowinPass : public ScriptPass
const std::vector<DSPRule> gw5a_dsp_rules = {
{27, 36, 2, 19, "$__MUL27X36"},
{27, 18, 13, 13, "$__MUL27X18"},
{27, 18, 13, 2, "$__MUL27X18"},
{12, 12, 2, 2, "$__MUL12X12"},
};

13
tests/arch/gowin/mul_gw5a.ys
View File

@ -37,6 +37,19 @@ cd top
select -assert-count 1 t:MULTALU27X18
# 4x13 -> 1 MULTALU27X18 (asymmetric: narrower operand below the 12x12 cell's
# width, yet the product fits one 27x18 tile; relies on operand-order
# normalization in mul2dsp plus B_MIN=2 on the 27x18 rule)
design -reset
read_verilog mul_gw5a.v
chparam -set X_WIDTH 4 -set Y_WIDTH 13 -set A_WIDTH 17
hierarchy -top top
proc
synth_gowin -family gw5a
cd top
select -assert-count 1 t:MULTALU27X18
# 28x18 -> A overflows 27: 1 MULTALU27X18 + MULT12X12 partials
design -reset
read_verilog mul_gw5a.v