yosys/techlibs/rapidflex/alkaidC/cell_sim.v

9 lines
267 B
Verilog

//-------------------------------------------------
// Include all the primitives
//-------------------------------------------------
`include "cell_sim_arith.v"
`include "cell_sim_ff.v"
`include "cell_sim_pcnt.v"
`include "ccb_inst_code.v"
`include "cell_sim_ccb.v"