mirror of https://github.com/YosysHQ/yosys.git
9 lines
267 B
Verilog
9 lines
267 B
Verilog
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//-------------------------------------------------
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// Include all the primitives
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//-------------------------------------------------
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`include "cell_sim_arith.v"
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`include "cell_sim_ff.v"
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`include "cell_sim_pcnt.v"
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`include "ccb_inst_code.v"
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`include "cell_sim_ccb.v"
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