Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 09:30:28 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
25ae2d4df0cf9fcd4069e66d260c207300415af9
yosys/techlibs
T
History
Clifford Wolf 29d6ebd961 Implemented technology mapping for multipliers (using array multiplier)
2013-06-03 12:48:44 +02:00
..
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
blackbox.sed
initial import
2013-01-05 11:13:26 +01:00
Makefile.inc
Added EXTRA_TARGETS Makefile variable
2013-03-28 16:53:40 +01:00
simlib.v
Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v
2013-04-07 16:42:29 +02:00
stdcells_sim.v
initial import
2013-01-05 11:13:26 +01:00
stdcells.v
Implemented technology mapping for multipliers (using array multiplier)
2013-06-03 12:48:44 +02:00
Powered by Gitea Version: 1.27.2 Page: 531ms Template: 34ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API