yosys/techlibs/quicklogic at 1336ca079e282578f76e35a60ef1696b6d51a76c - yosys - Gitea: Git with a cup of tea

luke/yosys

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Emil J. Tywoniak 6c048fdfb9 signorm: disable in passes that use swap_names

2026-09-17 14:13:57 +02:00

..

synth_quicklogic: rearrange files to prepare for adding more architectures

2023-12-04 15:52:02 +01:00

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

CMakeLists.txt

CMake: add missing dependency edges for synth_* passes.

2026-08-06 14:48:56 +00:00

ql_bram_merge.cc

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

ql_bram_types.cc

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

ql_dsp_io_regs.cc

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

ql_dsp_macc.cc

Fixing couple more conversion errors

2026-05-14 15:58:58 +02:00

ql_dsp_macc.pmg

ql_dsp_macc: Tune DSP inference code

2023-12-04 15:52:02 +01:00

ql_dsp_simd.cc

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

ql_ioff.cc

signorm: disable in passes that use swap_names

2026-09-17 14:13:57 +02:00

synth_quicklogic.cc

synth_quicklogic: remove classic ABC mapping

2026-08-19 11:42:59 +01:00