Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-30 18:01:44 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
1202f7aa4bb0f9afde157ebc4701d64e7e38abd8
yosys/passes/techmap
T
History
Clifford Wolf 1202f7aa4b Renamed "stdcells.v" to "techmap.v"
2014-07-31 02:32:00 +02:00
..
.gitignore
Renamed "stdcells.v" to "techmap.v"
2014-07-31 02:32:00 +02:00
dfflibmap.cc
Refactoring: Renamed RTLIL::Design::modules to modules_
2014-07-27 11:18:30 +02:00
extract.cc
Added "techmap -map %{design-name}"
2014-07-29 16:35:13 +02:00
filterlib.cc
Moved dfflibmap from passes/dfflibmap to passes/techmap
2013-10-16 15:32:26 +02:00
hilomap.cc
Refactoring: Renamed RTLIL::Design::modules to modules_
2014-07-27 11:18:30 +02:00
iopadmap.cc
Refactoring: Renamed RTLIL::Design::modules to modules_
2014-07-27 11:18:30 +02:00
libparse.cc
Fixed dumping of timing() { .. } block in libparse
2014-03-09 15:16:07 +01:00
libparse.h
renamed LibertyParer to LibertyParser
2014-01-14 18:57:47 +01:00
Makefile.inc
Renamed "stdcells.v" to "techmap.v"
2014-07-31 02:32:00 +02:00
simplemap.cc
Using log_assert() instead of assert()
2014-07-28 11:27:48 +02:00
techmap.cc
Renamed "stdcells.v" to "techmap.v"
2014-07-31 02:32:00 +02:00
Powered by Gitea Version: 1.27.2 Page: 2483ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API