Emil J. Tywoniak 0f3efd2c1a fixup! memory_bram: add -register		2026-03-31 14:59:34 +02:00
..
cmds	sort: init	2026-03-27 15:13:47 +01:00
equiv	signorm: disable passes that use rewrite_sigspecs	2026-03-17 17:35:57 +01:00
fsm	Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix()	2025-09-16 23:02:16 +00:00
hierarchy	flatten: redo signormalization to work around fanout issue	2026-03-17 18:04:41 +01:00
memory	fixup! memory_bram: add -register	2026-03-31 14:59:34 +02:00
opt	Move `Design::sort()` calls out of `opt` and `opt_clean` passes into the synth passes that need them.	2026-03-27 15:16:08 +01:00
pmgen	Remove .c_str() from log_cmd_error() and log_file_error() parameters	2025-09-16 22:59:08 +00:00
proc	Update passes/proc to avoid bits()	2025-09-16 03:17:23 +00:00
sat	signorm: disable passes that use rewrite_sigspecs	2026-03-17 17:35:57 +01:00
techmap	techmap: read_verilog -icells, I mean, obviously	2026-03-24 23:25:42 +01:00
tests	Remove .c_str() from parameters to log_debug()	2025-09-23 19:10:33 +12:00