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yosys/techlibs
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nella 77bca709d4 Declare synth_fabulous pad cells as blackboxes. 
iopadmap inserted $__FABULOUS_* cells with no module, so their port
directions were unknown to later passes. Read with -icells so the module
names match the cell types.
2026-09-14 13:50:09 +02:00
..
achronix
synth_achronix: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
analogdevices
synth*: run check after proc before opt_clean to discover process-initial driver conflicts
2026-09-02 14:44:36 +02:00
anlogic
synth_anlogic: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
common
prep: also sequence checks better
2026-09-02 15:13:39 +02:00
easic
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
efinix
synth_efinix: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
fabulous
Declare synth_fabulous pad cells as blackboxes.
2026-09-14 13:50:09 +02:00
gatemate
synth*: run check after proc before opt_clean to discover process-initial driver conflicts
2026-09-02 14:44:36 +02:00
gowin
synth*: run check after proc before opt_clean to discover process-initial driver conflicts
2026-09-02 14:44:36 +02:00
ice40
synth*: run check after proc before opt_clean to discover process-initial driver conflicts
2026-09-02 14:44:36 +02:00
intel
synth*: run check after proc before opt_clean to discover process-initial driver conflicts
2026-09-02 14:44:36 +02:00
intel_alm
synth*: run check after proc before opt_clean to discover process-initial driver conflicts
2026-09-02 14:44:36 +02:00
lattice
synth*: run check after proc before opt_clean to discover process-initial driver conflicts
2026-09-02 14:44:36 +02:00
microchip
synth*: run check after proc before opt_clean to discover process-initial driver conflicts
2026-09-02 14:44:36 +02:00
nanoxplore
synth*: run check after proc before opt_clean to discover process-initial driver conflicts
2026-09-02 14:44:36 +02:00
quicklogic
synth*: run check after proc before opt_clean to discover process-initial driver conflicts
2026-09-02 14:44:36 +02:00
sf2
synth_sf2: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
xilinx
synth*: run check after proc before opt_clean to discover process-initial driver conflicts
2026-09-02 14:44:36 +02:00
CMakeLists.txt
Merge pull request #6132 from YosysHQ/lofty/abc-refactor-12
2026-08-19 10:19:14 +00:00
fix_mod.py
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00