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yosys/techlibs/intel
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Miodrag Milanovic 0dfbd13fe7 Use read_techlib where applicable 2026-06-12 10:01:24 +02:00
..
common Fixed data/address width parameters 2024-03-06 02:45:07 +01:00
cyclone10lp Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
cycloneiv Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
cycloneive Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
max10 Removed SystemVerilog module end label 2024-03-19 01:31:36 +01:00
CMakeLists.txt Use read_techlib where applicable 2026-06-12 10:01:24 +02:00
synth_intel.cc Use read_techlib where applicable 2026-06-12 10:01:24 +02:00