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Use read_techlib where applicable

This commit is contained in:
Miodrag Milanovic 2026-06-12 10:01:24 +02:00
parent cf316ad85e
commit 0dfbd13fe7
38 changed files with 64 additions and 64 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
passes/techmap/abc9.cc
View File

@ -342,7 +342,7 @@ struct Abc9Pass : public ScriptPass
}
if (check_label("pre")) {
run("read_verilog -icells -lib -specify +/abc9_model.v");
run("read_techlib -icells -lib -specify +/abc9_model.v");
if (help_mode)
run("abc9_ops -break_scc -prep_delays -prep_xaiger [-dff]", "(option for -dff)");
else

12
passes/techmap/techmap.cc
View File

@ -1149,7 +1149,7 @@ struct TechmapPass : public Pass {
std::vector<std::string> map_files;
std::vector<RTLIL::IdString> dont_map;
std::string verilog_frontend = "verilog -nooverwrite -noblackbox -icells";
std::string techlib_frontend = "techlib -nooverwrite -noblackbox -icells";
int max_iter = -1;
size_t argidx;
@ -1163,15 +1163,15 @@ struct TechmapPass : public Pass {
continue;
}
if (args[argidx] == "-D" && argidx+1 < args.size()) {
verilog_frontend += " -D " + args[++argidx];
techlib_frontend += " -D " + args[++argidx];
continue;
}
if (args[argidx] == "-I" && argidx+1 < args.size()) {
verilog_frontend += " -I " + args[++argidx];
techlib_frontend += " -I " + args[++argidx];
continue;
}
if (args[argidx] == "-relativeshare") {
verilog_frontend += " -relativeshare";
techlib_frontend += " -relativeshare";
log_experimental("techmap -relativeshare");
continue;
}
@ -1205,7 +1205,7 @@ struct TechmapPass : public Pass {
RTLIL::Design *map = new RTLIL::Design;
if (map_files.empty()) {
Frontend::frontend_call(map, nullptr, "+/techmap.v", verilog_frontend);
Frontend::frontend_call(map, nullptr, "+/techmap.v", techlib_frontend);
} else {
for (auto &fn : map_files)
if (fn.compare(0, 1, "%") == 0) {
@ -1217,7 +1217,7 @@ struct TechmapPass : public Pass {
if (!map->module(mod->name))
map->add(mod->clone());
} else {
Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : verilog_frontend));
Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : techlib_frontend));
}
}

2
techlibs/achronix/CMakeLists.txt
View File

@ -13,7 +13,7 @@ yosys_pass(synth_achronix
memory_map
opt
proc
read_verilog
read_techlib
setundef
stat
synth

2
techlibs/achronix/synth_achronix.cc
View File

@ -122,7 +122,7 @@ struct SynthAchronixPass : public ScriptPass {
{
if (check_label("begin"))
{
run("read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v");
run("read_techlib -sv -lib +/achronix/speedster22i/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}

2
techlibs/analogdevices/CMakeLists.txt
View File

@ -27,7 +27,7 @@ yosys_pass(synth_analogdevices
peepopt
pmux2shiftx
proc
read_verilog
read_techlib
select
setattr
share

4
techlibs/analogdevices/synth_analogdevices.cc
View File

@ -271,7 +271,7 @@ struct SynthAnalogDevicesPass : public ScriptPass
void script() override
{
if (check_label("begin")) {
run(stringf("read_verilog -lib -specify %s +/analogdevices/cells_sim.v", tech_param));
run(stringf("read_techlib -lib -specify %s +/analogdevices/cells_sim.v", tech_param));
run(stringf("hierarchy -check %s", top_opt.c_str()));
}
@ -456,7 +456,7 @@ struct SynthAnalogDevicesPass : public ScriptPass
if (help_mode)
run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')");
else if (abc9) {
run("read_verilog -icells -lib -specify +/analogdevices/abc9_model.v");
run("read_techlib -icells -lib -specify +/analogdevices/abc9_model.v");
std::string abc9_opts;
std::string k = "synth_analogdevices.abc9.W";
if (active_design && active_design->scratchpad.count(k))

2
techlibs/anlogic/CMakeLists.txt
View File

@ -23,7 +23,7 @@ yosys_pass(synth_anlogic
opt
opt_expr
proc
read_verilog
read_techlib
simplemap
stat
synth

2
techlibs/anlogic/synth_anlogic.cc
View File

@ -149,7 +149,7 @@ struct SynthAnlogicPass : public ScriptPass
{
if (check_label("begin"))
{
run("read_verilog -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v");
run("read_techlib -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}

2
techlibs/coolrunner2/CMakeLists.txt
View File

@ -24,7 +24,7 @@ yosys_pass(synth_coolrunner2
iopadmap
opt
proc
read_verilog
read_techlib
splitnets
stat
synth

2
techlibs/coolrunner2/synth_coolrunner2.cc
View File

@ -125,7 +125,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
{
if (check_label("begin"))
{
run("read_verilog -lib +/coolrunner2/cells_sim.v");
run("read_techlib -lib +/coolrunner2/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}

2
techlibs/efinix/CMakeLists.txt
View File

@ -20,7 +20,7 @@ yosys_pass(synth_efinix
opt
opt_expr
proc
read_verilog
read_techlib
simplemap
stat
synth

2
techlibs/efinix/synth_efinix.cc
View File

@ -141,7 +141,7 @@ struct SynthEfinixPass : public ScriptPass
{
if (check_label("begin"))
{
run("read_verilog -lib +/efinix/cells_sim.v");
run("read_techlib -lib +/efinix/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}

2
techlibs/fabulous/CMakeLists.txt
View File

@ -19,7 +19,7 @@ yosys_pass(synth_fabulous
opt_expr
peepopt
proc
read_verilog
read_techlib
share
stat
techmap

8
techlibs/fabulous/synth_fabulous.cc
View File

@ -261,14 +261,14 @@ struct SynthPass : public ScriptPass
void script() override
{
if (plib.empty())
run(stringf("read_verilog %s -lib +/fabulous/prims.v", complexdff ? "-DCOMPLEX_DFF" : ""));
run(stringf("read_techlib %s -lib +/fabulous/prims.v", complexdff ? "-DCOMPLEX_DFF" : ""));
else
run("read_verilog -lib " + plib);
run("read_techlib -lib " + plib);
if (help_mode) {
run("read_verilog -lib <extra_plib.v>", "(for each -extra-plib)");
run("read_techlib -lib <extra_plib.v>", "(for each -extra-plib)");
} else for (auto lib : extra_plib) {
run("read_verilog -lib " + lib);
run("read_techlib -lib " + lib);
}
if (check_label("begin")) {

2
techlibs/gatemate/CMakeLists.txt
View File

@ -36,7 +36,7 @@ yosys_pass(synth_gatemate
opt_expr
peepopt
proc
read_verilog
read_techlib
share
simplemap
stat

2
techlibs/gatemate/synth_gatemate.cc
View File

@ -219,7 +219,7 @@ struct SynthGateMatePass : public ScriptPass
{
if (check_label("begin"))
{
run("read_verilog -lib -specify +/gatemate/cells_sim.v +/gatemate/cells_bb.v");
run("read_techlib -lib -specify +/gatemate/cells_sim.v +/gatemate/cells_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}

2
techlibs/gowin/CMakeLists.txt
View File

@ -24,7 +24,7 @@ yosys_pass(synth_gowin
opt_lut_ins
peepopt
proc
read_verilog
read_techlib
setundef
share
simplemap

8
techlibs/gowin/synth_gowin.cc
View File

@ -257,8 +257,8 @@ struct SynthGowinPass : public ScriptPass
if (check_label("begin"))
{
run("read_verilog -specify -lib +/gowin/cells_sim.v");
run(stringf("read_verilog -specify -lib +/gowin/cells_xtra_%s.v", help_mode ? "<family>" : family));
run("read_techlib -specify -lib +/gowin/cells_sim.v");
run(stringf("read_techlib -specify -lib +/gowin/cells_xtra_%s.v", help_mode ? "<family>" : family));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
@ -362,12 +362,12 @@ struct SynthGowinPass : public ScriptPass
{
run("sort");
if (nowidelut && abc9) {
run("read_verilog -icells -lib -specify +/abc9_model.v");
run("read_techlib -icells -lib -specify +/abc9_model.v");
run("abc9 -maxlut 4 -W 500");
} else if (nowidelut && !abc9) {
run("abc -lut 4");
} else if (!nowidelut && abc9) {
run("read_verilog -icells -lib -specify +/abc9_model.v");
run("read_techlib -icells -lib -specify +/abc9_model.v");
run("abc9 -maxlut 8 -W 500");
} else if (!nowidelut && !abc9) {
run("abc -lut 4:8");

2
techlibs/greenpak4/CMakeLists.txt
View File

@ -21,7 +21,7 @@ yosys_pass(synth_greenpak4
nlutmap
opt
proc
read_verilog
read_techlib
shregmap
stat
synth

2
techlibs/greenpak4/synth_greenpak4.cc
View File

@ -137,7 +137,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
{
if (check_label("begin"))
{
run("read_verilog -lib +/greenpak4/cells_sim.v");
run("read_techlib -lib +/greenpak4/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}

2
techlibs/ice40/CMakeLists.txt
View File

@ -55,7 +55,7 @@ yosys_pass(synth_ice40
opt_lut
peepopt
proc
read_verilog
read_techlib
select
setattr
share

4
techlibs/ice40/synth_ice40.cc
View File

@ -301,7 +301,7 @@ struct SynthIce40Pass : public ScriptPass
if (check_label("begin"))
{
run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v");
run("read_techlib " + define + " -lib -specify +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
run("proc");
}
@ -416,7 +416,7 @@ struct SynthIce40Pass : public ScriptPass
}
if (!noabc) {
if (abc9) {
run("read_verilog " + define + " -icells -lib -specify +/ice40/abc9_model.v");
run("read_techlib " + define + " -icells -lib -specify +/ice40/abc9_model.v");
std::string abc9_opts;
std::string k = "synth_ice40.abc9.W";
if (active_design && active_design->scratchpad.count(k))

2
techlibs/intel/CMakeLists.txt
View File

@ -21,7 +21,7 @@ yosys_pass(synth_intel
opt_expr
peepopt
proc
read_verilog
read_techlib
setundef
stat
techmap

6
techlibs/intel/synth_intel.cc
View File

@ -188,11 +188,11 @@ struct SynthIntelPass : public ScriptPass {
{
if (check_label("begin")) {
if (check_label("family"))
run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt));
run(stringf("read_techlib -sv -lib +/intel/%s/cells_sim.v", family_opt));
// Misc and common cells
run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
run("read_techlib -sv -lib +/intel/common/m9k_bb.v");
run("read_techlib -sv -lib +/intel/common/altpll_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}

2
techlibs/intel_alm/CMakeLists.txt
View File

@ -22,7 +22,7 @@ yosys_pass(synth_intel_alm
opt_expr
peepopt
proc
read_verilog
read_techlib
share
stat
techmap

18
techlibs/intel_alm/synth_intel_alm.cc
View File

@ -169,16 +169,16 @@ struct SynthIntelALMPass : public ScriptPass {
if (check_label("begin")) {
if (family_opt == "cyclonev")
run(stringf("read_verilog -sv -lib +/intel_alm/%s/cells_sim.v", family_opt));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dsp_sim.v", family_opt));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/misc_sim.v", family_opt));
run(stringf("read_verilog -specify -lib -D %s -icells +/intel_alm/common/abc9_model.v", family_opt));
run(stringf("read_techlib -sv -lib +/intel_alm/%s/cells_sim.v", family_opt));
run(stringf("read_techlib -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt));
run(stringf("read_techlib -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt));
run(stringf("read_techlib -specify -lib -D %s +/intel_alm/common/dsp_sim.v", family_opt));
run(stringf("read_techlib -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt));
run(stringf("read_techlib -specify -lib -D %s +/intel_alm/common/misc_sim.v", family_opt));
run(stringf("read_techlib -specify -lib -D %s -icells +/intel_alm/common/abc9_model.v", family_opt));
// Misc and common cells
run("read_verilog -lib +/intel/common/altpll_bb.v");
run("read_verilog -lib +/intel_alm/common/megafunction_bb.v");
run("read_techlib -lib +/intel/common/altpll_bb.v");
run("read_techlib -lib +/intel_alm/common/megafunction_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}

2
techlibs/lattice/CMakeLists.txt
View File

@ -40,7 +40,7 @@ yosys_pass(synth_lattice
opt_merge
peepopt
proc
read_verilog
read_techlib
share
simplemap
stat

2
techlibs/lattice/synth_lattice.cc
View File

@ -395,7 +395,7 @@ struct SynthLatticePass : public ScriptPass
if (check_label("begin"))
{
run("read_verilog -lib -specify +/lattice/cells_sim" + postfix + ".v +/lattice/cells_bb" + postfix + ".v");
run("read_techlib -lib -specify +/lattice/cells_sim" + postfix + ".v +/lattice/cells_bb" + postfix + ".v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}

2
techlibs/microchip/CMakeLists.txt
View File

@ -47,7 +47,7 @@ yosys_pass(synth_microchip
opt_expr
peepopt
proc
read_verilog
read_techlib
select
setattr
share

2
techlibs/microchip/synth_microchip.cc
View File

@ -260,7 +260,7 @@ struct SynthMicrochipPass : public ScriptPass {
if (check_label("begin")) {
std::string read_args;
read_args += " -lib -specify +/microchip/cells_sim.v";
run("read_verilog" + read_args);
run("read_techlib" + read_args);
run(stringf("hierarchy -check %s", top_opt));
}

2
techlibs/nanoxplore/CMakeLists.txt
View File

@ -27,7 +27,7 @@ yosys_pass(synth_nanoxplore
opt_merge
peepopt
proc
read_verilog
read_techlib
setundef
share
stat

2
techlibs/nanoxplore/synth_nanoxplore.cc
View File

@ -241,7 +241,7 @@ struct SynthNanoXplorePass : public ScriptPass
if (check_label("begin"))
{
run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim" + postfix + ".v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v");
run("read_techlib -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim" + postfix + ".v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v");
run("techmap -map +/nanoxplore/cells_wrap.v");
run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));

2
techlibs/quicklogic/CMakeLists.txt
View File

@ -63,7 +63,7 @@ yosys_pass(synth_quicklogic
ql_dsp_macc
ql_dsp_simd
ql_ioff
read_verilog
read_techlib
setundef
share
shregmap

4
techlibs/quicklogic/synth_quicklogic.cc
View File

@ -198,7 +198,7 @@ struct SynthQuickLogicPass : public ScriptPass {
}
if (check_label("begin")) {
std::string read_simlibs = stringf("read_verilog -lib -specify %scommon/cells_sim.v %s%s/cells_sim.v", lib_path, lib_path, family);
std::string read_simlibs = stringf("read_techlib -lib -specify %scommon/cells_sim.v %s%s/cells_sim.v", lib_path, lib_path, family);
if (family == "qlf_k6n10f") {
read_simlibs += stringf(" %sqlf_k6n10f/brams_sim.v", lib_path);
if (bramTypes)
@ -317,7 +317,7 @@ struct SynthQuickLogicPass : public ScriptPass {
if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) {
run("techmap -map " + lib_path + family + "/latches_map.v");
if (abc9) {
run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v");
run("read_techlib -lib -specify -icells " + lib_path + family + "/abc9_model.v");
run("techmap -map " + lib_path + family + "/abc9_map.v");
run("abc9 -maxlut 4 -dff");
run("techmap -map " + lib_path + family + "/abc9_unmap.v");

2
techlibs/sf2/CMakeLists.txt
View File

@ -16,7 +16,7 @@ yosys_pass(synth_sf2
opt
opt_expr
proc
read_verilog
read_techlib
simplemap
stat
synth

2
techlibs/sf2/synth_sf2.cc
View File

@ -165,7 +165,7 @@ struct SynthSf2Pass : public ScriptPass
{
if (check_label("begin"))
{
run("read_verilog -lib +/sf2/cells_sim.v");
run("read_techlib -lib +/sf2/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}

2
techlibs/xilinx/CMakeLists.txt
View File

@ -58,7 +58,7 @@ yosys_pass(synth_xilinx
peepopt
pmux2shiftx
proc
read_verilog
read_techlib
select
setattr
share

6
techlibs/xilinx/synth_xilinx.cc
View File

@ -346,9 +346,9 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("begin")) {
std::string read_args;
read_args += " -lib -specify +/xilinx/cells_sim.v";
run("read_verilog" + read_args);
run("read_techlib" + read_args);
run("read_verilog -lib +/xilinx/cells_xtra.v");
run("read_techlib -lib +/xilinx/cells_xtra.v");
run(stringf("hierarchy -check %s", top_opt));
}
@ -651,7 +651,7 @@ struct SynthXilinxPass : public ScriptPass
if (family != "xc7")
log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
"will use timing for 'xc7' instead.\n", family.c_str());
run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v");
run("read_techlib -icells -lib -specify +/xilinx/abc9_model.v");
std::string abc9_opts;
std::string k = "synth_xilinx.abc9.W";
if (active_design && active_design->scratchpad.count(k))