mirror of https://github.com/YosysHQ/yosys.git
8c7b1921d2
process_module() could hit the modules_.count(module->name) == 0 assertion in Design::add() when a module gets reprocessed via AstModule::reprocess_if_necessary(). This happens for a parameterized module that instantiates a submodule inside a generate block, where the submodule only becomes available after the enclosing module's initial derivation. In that case, process_module() could attempt to register a module under a name that was already occupied. Guard the design add call in process_module() by removing any stale module already registered under the target name before adding the newly generated one. Verified against the reproduction case in issue #6002 (multiply elaborates successfully without crashing) and confirmed the previously working divide case produces identical output before and after this change. Fixes #6002 |
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| aiger | ||
| aiger2 | ||
| ast | ||
| blif | ||
| json | ||
| liberty | ||
| rpc | ||
| rtlil | ||
| slang | ||
| verific | ||
| verilog | ||
| CMakeLists.txt | ||