luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
17,572 Commits 137 Branches 69 Tags 54 MiB
Commit Graph

2112 Commits

Author SHA1 Message Date
Greeshma Manjegowda 8c7b1921d2 ast: guard against module name collision during reprocessing 
process_module() could hit the modules_.count(module->name) == 0
assertion in Design::add() when a module gets reprocessed via
AstModule::reprocess_if_necessary(). This happens for a
parameterized module that instantiates a submodule inside a
generate block, where the submodule only becomes available after
the enclosing module's initial derivation. In that case,
process_module() could attempt to register a module under a name
that was already occupied.

Guard the design add call in process_module() by removing any
stale module already registered under the target name before
adding the newly generated one.

Verified against the reproduction case in issue #6002 (multiply
elaborates successfully without crashing) and confirmed the
previously working divide case produces identical output before
and after this change.

Fixes #6002
 2026-07-24 17:30:01 -05:00
Miodrag Milanovic eb3a15cd8c Update sv-elab to 3dddccd 2026-07-15 08:24:46 +02:00
Miodrag Milanovic 30ba4328e7 Use system libs when available 2026-07-13 15:26:00 +02:00
Michael Baier 8f0028652a long long to int truncation checks 2026-07-10 14:36:39 +02:00
Michael Baier eb4e29810e Fixed Overflow error in checking width 2026-07-09 14:34:56 +02:00
Michael Baier 42092cbc77 Adding width checks to frontend 2026-07-09 14:34:56 +02:00
Lofty 75286287c6
Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7 
Move rename logic to abc_ops_reintegrate
 2026-07-09 08:46:46 +00:00
Martin Povišer ff8a867764 Bump sv-elab to 2026-07-07 2026-07-07 15:20:19 +02:00
Miodrag Milanovic 05c0adae77 Slang frontend integration 2026-07-06 15:49:56 +02:00
Miodrag Milanovic a689342207 Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
Miodrag Milanovic 48a3dcc02a End of file fix 2026-06-23 07:23:41 +02:00
Lofty 091d2a7814 Move rename logic to abc_ops_reintegrate 2026-06-19 10:46:47 +01:00
nella 5d7486115a
Merge pull request #5887 from YosysHQ/nella/fix-signedness-4402 
Fix: `read_verilog` doesn't respect `signed` keyword
 2026-06-18 16:53:37 +00:00
Krystine Sherwin b79c7c008d
simplify.cc: Fix crash when identifier matches module 
Also update one of the AST debug prints that is guarded by an `#if 0` but was out of date.
 2026-06-12 11:54:53 +12:00
Lofty 73c217133b
Merge pull request #5934 from YosysHQ/lofty/abc9-refactor-5 
read_aiger: import standard-cell mappings from ABC
 2026-06-08 09:38:34 +00:00
Lofty 2a4525efbb read_aiger: import standard-cell mappings from ABC 2026-06-05 11:02:58 +01:00
Miodrag Milanovic 102f008194 Remove EMSCRIPTEN leftovers 2026-06-05 10:03:27 +02:00
Miodrag Milanovic 5f2456ac03 WASI now support filesystem 2026-06-05 09:18:00 +02:00
Miodrag Milanović 693d5a7eb0
Merge pull request #5903 from YosysHQ/krys/verific_memsize 
verific: Fix non-contiguous memory flattening producing out of bounds accesses in some cases
 2026-06-04 05:43:04 +00:00
Miodrag Milanovic ce280354cf Update CI scripts for CMake 
Co-authored-by: Catherine <whitequark@whitequark.org>
 2026-06-03 08:58:11 +00:00
Catherine a727e7f6e7 Migrate build system to CMake 
See #5895 for details.

This commit does not include CI or documentation changes.
 2026-06-03 08:58:10 +00:00
Emil J. Tywoniak 80bdbaa010 genrtlil: don't avoid emitting flops for nosync 2026-05-29 11:37:08 +02:00
Krystine Sherwin 5f53410db7
verific: Fix negative array dimensions 
Recurse over memory dimensions once, doing both our min/max address checking and parsing out the initval.  This also avoids problems with negative numbers (if `a < b` and one or both are negative, `a` might be the intended `max_addr_chunk`).
Fix sub addressing, where we use some but not all of the current dimension's bits.
 2026-05-29 18:40:25 +12:00
Krystine Sherwin 21966ef496
verific: Fix non-contiguous memory init 
Recurse over nested type ranges to calculate true addresses.
 2026-05-29 18:40:25 +12:00
Krystine Sherwin 099c664dc9
verific: Fix upto ranges 2026-05-29 18:40:23 +12:00
Krystine Sherwin 7cf0c55466
verific: Fix non-contiguous memory flattening 
May not be the best approach, insofar as it uses empty memory elements for padding out the alignment, but it does avoid costly address arithmetic.
Still needs to adjust ascii init val addresses, but should work fine for read/write accesses.
 2026-05-29 18:40:23 +12:00
Miodrag Milanovic 75dcbe03c6 Convert RTLIL::unescape_id of IdString to unescape() 2026-05-16 19:49:45 +02:00
Miodrag Milanovic 8bbc3c359c Remove id2cstr uses in our code base 2026-05-16 19:49:45 +02:00
Miodrag Milanovic 4a7878b17f Fixing couple more conversion errors 2026-05-14 15:58:58 +02:00
Miodrag Milanovic 9580ebabc5 log_id here was needed for unescaping 2026-05-14 12:35:01 +02:00
nella 38c2806636 Make sure to apply correct signedness to loop vars. 2026-05-13 16:52:07 +02:00
Codexplorer e41b969da2 Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
Christopher D. Leary 390f09b89a Support positional assignment patterns for unpacked arrays 2026-04-23 14:29:38 -07:00
Petter Reinholdtsen a89e8fd869 Fixed spelling error in message of frontends/ast/genrtlil.cc. 
Patch by Ruben Undheim via the Debian project.  The patch originated
as 0009-Some-spelling-errors-fixed.patch and was dated 2018-07-12
there.

See also issue #5805.
 2026-04-22 04:30:18 +02:00
Lofty ed5d122174
Merge pull request #5793 from YosysHQ/lofty/abc-refactor-4 
read/write_xaiger2: further cleanup [sc-269]
 2026-04-21 12:13:42 +00:00
Emil J 86448c0001
Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef 
Undefine set&reset behavior of $dffsr
 2026-04-08 14:22:34 +00:00
Lofty 6d715784cd read_xaiger2: further cleanup 2026-04-08 11:08:59 +01:00
Emil J. Tywoniak ad7a776d73 genrtlil: even faster removeSignalFromCaseTree 2026-03-18 23:33:35 +01:00
Emil J. Tywoniak 23ce4b8560 genrtlil: faster removeSignalFromCaseTree 2026-03-18 23:33:35 +01:00
Emil J. Tywoniak 85013f9ed3 fixup! read_liberty: model clear_preset_variable correctly 2026-03-06 14:24:18 +01:00
Robert O'Callahan 13d9fffdb9 Work around `std::reverse` miscompilation with empty range 
This causes problems when compiling with fuzzing instrumenation enabled.
 2026-03-06 02:03:21 +00:00
Emil J 629bf3dffd
Merge pull request #5630 from apullin/array-assignment 
ast: Add support for array-to-array assignment
 2026-03-05 11:10:12 +00:00
Andrew Pullin 6ac8c8cb05 ast: Add support for array-to-array assignment 
This commit adds support for SystemVerilog array-to-array assignment
operations that were previously unsupported:

1. Direct array assignment: `b = a;`
2. Array ternary expressions: `out = sel ? a : b;`

Both single-dimensional and multi-dimensional unpacked arrays are
supported. The implementation expands these array operations during
AST simplification into element-wise assignments.

Example of now-supported syntax:
```systemverilog
wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;
```

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
 2026-03-04 21:34:40 -08:00
Emil J 0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes 
celltypes: compile-time lookup tables for internal cells
 2026-03-04 14:47:57 +00:00
Emil J. Tywoniak ecb8b20f62 yosys: use newcelltypes for yosys_celltypes users 2026-03-04 12:39:44 +01:00
Emil J. Tywoniak 126492742b read_liberty: fix for msvc 2026-03-03 17:34:58 +01:00
Emil J. Tywoniak 22916aaab1 read_liberty: model clear_preset_variable correctly 2026-03-03 10:35:03 +01:00
Emil J. Tywoniak 857bc02710 liberty: warn if dffsr has clear&preset well defined 2026-03-03 10:34:29 +01:00
likeamahoney e9442194f2 support automatic lifetime qualifier on procedural variables 2026-02-27 20:42:52 +03:00
Emil J 13795203a1
Merge pull request #5680 from YosysHQ/emi/aiger-add-bounds-checks 
aigerparse: add some bounds checks
 2026-02-20 11:53:49 +01:00