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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 20:12:09 +02:00
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itsaflower-patch-2
yosys/frontends/verilog
T
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Emil J 85acd07685 Merge pull request #6123 from sifferman/fix-resetall-default-nettype
Fix resetall not affecting default_nettype
2026-08-24 09:47:04 +00:00
..
.gitignore
read_verilog, ast: use unified locations in errors and simplify dependencies
2025-08-11 13:34:10 +02:00
CMakeLists.txt
[core] add a cmake option to disable unit test during compilation; Use cmake_current_source for submodule integration
2026-08-21 12:09:04 -07:00
const2ast.cc
Attr file:line.
2026-07-31 10:31:44 +02:00
preproc.cc
reset default_nettype on `resetall for the lexer
2026-08-16 14:26:21 -07:00
preproc.h
reset default_nettype on `resetall for the lexer
2026-08-16 14:26:21 -07:00
verilog_error.cc
Use C++ stringf machinery in verilog_error
2025-09-12 06:21:56 +00:00
verilog_error.h
Use C++ stringf machinery in verilog_error
2025-09-12 06:21:56 +00:00
verilog_frontend.cc
reset default_nettype on `resetall for the lexer
2026-08-16 14:26:21 -07:00
verilog_frontend.h
Clean up diagnostics.
2026-07-31 10:31:44 +02:00
verilog_lexer.h
verilog_lexer: refactor
2025-08-11 13:34:10 +02:00
verilog_lexer.l
End of file fix
2026-06-23 07:23:41 +02:00
verilog_location.h
verilog: Fix missing sstream include
2025-08-21 08:26:20 +01:00
verilog_parser.y
Support positional assignment patterns for unpacked arrays
2026-04-23 14:29:38 -07:00
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