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yosys/techlibs/xilinx
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Emil J. Tywoniak b3c7a25be5 techlibs: trivial twine damage
2026-08-13 18:15:58 +02:00
..
tests
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
abc9_model.v
…
arith_map.v
End of file fix
2026-06-23 07:23:41 +02:00
brams_defs.vh
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xc2v_map.v
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xc2v.txt
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xc3sda_map.v
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xc3sda.txt
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xc4v_map.v
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xc4v.txt
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xc5v_map.v
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xc6v_map.v
Fix RAMB36E1/E2 SDP parity port mapping typo
2026-04-18 19:10:18 +03:00
brams_xcu_map.v
End of file fix
2026-06-23 07:23:41 +02:00
brams_xcv_map.v
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams_xcv.txt
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
cells_map.v
Clearer diff for the all-x corner case
2025-04-07 07:55:30 +02:00
cells_sim.v
Update Xilinx cell definitions, fixes #3699
2023-03-23 09:44:36 +01:00
cells_xtra.py
Update Xilinx cell definitions, fixes #3699
2023-03-23 09:44:36 +01:00
cells_xtra.v
End of file fix
2026-06-23 07:23:41 +02:00
CMakeLists.txt
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
ff_map.v
End of file fix
2026-06-23 07:23:41 +02:00
lut_map.v
End of file fix
2026-06-23 07:23:41 +02:00
lutrams_xc5v_map.v
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
lutrams_xc5v.txt
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
lutrams_xcu.txt
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
lutrams_xcv_map.v
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
lutrams_xcv.txt
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
mux_map.v
…
synth_xilinx.cc
Add check before flatten in synth_*.
2026-05-05 14:06:58 +02:00
urams_map.v
URAM mapping : Fix port indexes according to Yosys warnings
2025-05-09 15:09:11 +02:00
urams.txt
URAM mapping : Add test for 2048 x 144b
2025-05-10 14:53:56 +02:00
xc3s_mult_map.v
End of file fix
2026-06-23 07:23:41 +02:00
xc3sda_dsp_map.v
End of file fix
2026-06-23 07:23:41 +02:00
xc4v_dsp_map.v
…
xc5v_dsp_map.v
End of file fix
2026-06-23 07:23:41 +02:00
xc6s_dsp_map.v
End of file fix
2026-06-23 07:23:41 +02:00
xc7_dsp_map.v
…
xcu_dsp_map.v
End of file fix
2026-06-23 07:23:41 +02:00
xilinx_dffopt.cc
End of file fix
2026-06-23 07:23:41 +02:00
xilinx_dsp48a.pmg
pmgen: Move passes out of pmgen folder
2025-01-31 15:18:28 +13:00
xilinx_dsp_cascade.pmg
Refactor uses of log_id in pgm files
2026-05-14 12:21:32 +02:00
xilinx_dsp_CREG.pmg
pmgen: Move passes out of pmgen folder
2025-01-31 15:18:28 +13:00
xilinx_dsp.cc
techlibs: trivial twine damage
2026-08-13 18:15:58 +02:00
xilinx_dsp.pmg
Add support for subtraction in preadder
2026-02-03 08:31:01 -08:00
xilinx_srl.cc
xilinx_srl: keep the clock enable on FDRE shift registers
2026-07-20 23:59:40 -07:00
xilinx_srl.pmg
techlibs: trivial twine damage
2026-08-13 18:15:58 +02:00