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luke/yosys
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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 01:24:25 +02:00
Code Issues Packages Projects Releases Wiki Activity
14,136 Commits 148 Branches 70 Tags
0.46
Commit Graph
11 Commits
Author SHA1 Message Date
Miodrag Milanovic ad48639cdd Start restoring memory state from VCD/FST 2022-05-04 10:41:04 +02:00
Miodrag Milanovic 2e47b61cc6 Proper scope naming from FST 2022-03-30 15:55:15 +02:00
Miodrag Milanovic 1f3423cd7d Recognize registers and set initial state for them in tb 2022-03-16 14:35:39 +01:00
Miodrag Milanovic 8be09b5b24 VCD reader support by using external tool 2022-02-28 09:09:07 +01:00
Miodrag Milanovic fb22d7cdc4 Add support for various ff/latch cells simulation 2022-02-16 13:27:59 +01:00
Miodrag Milanovic 543feb75cb Display simulation time data 2022-01-31 10:52:47 +01:00
Miodrag Milanovic a8d03df173 cleanup 2022-01-28 12:54:16 +01:00
Miodrag Milanovic 4f75a2ca1b Do actual compare 2022-01-28 12:50:41 +01:00
Miodrag Milanovic 3e35de2be1 Add more options and time handling 2022-01-28 10:18:02 +01:00
Miodrag Milanovic 226dc659f0 Fix tabs/spaces 2022-01-26 16:39:51 +01:00
Miodrag Milanovic 8a02616465 Add fstdata helper class 2022-01-26 10:23:38 +01:00
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