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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 03:13:21 +02:00
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3,827 Commits 153 Branches 70 Tags
fe80b39f56fb650cc67bed09f29ea42e0e5f6e52
Commit Graph
8 Commits
Author SHA1 Message Date
Clifford Wolf b4c1d3084f Add "synth_intel --noiopads"
Signed-off-by: Clifford Wolf <[email protected]>
2018-04-30 13:02:56 +02:00
c60k28 efed2420d6 Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device 2018-03-31 22:48:47 -06:00
Clifford Wolf 9ac560f5d3 Add "dffinit -highlow" and fix synth_intel
Signed-off-by: Clifford Wolf <[email protected]>
2018-01-09 18:42:19 +01:00
dh73 3fd1d61e2a Initial Cyclone 10 support 2017-11-08 22:45:21 -06:00
Larry Doolittle 50bcd9a728 Clean whitespace and permissions in techlibs/intel 2017-10-05 16:23:49 +02:00
Clifford Wolf 65f91e5120 Rename "write_verilog -nobasenradix" to "write_verilog -decimal" 2017-10-03 17:31:21 +02:00
dh73 4718e65763 Tested and working altsyncarm without init files 2017-10-01 19:59:45 -05:00
dh73 cbaba62401 Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now 2017-10-01 11:04:17 -05:00
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