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Author SHA1 Message Date
Akash Levy 1f00bf0057 Bump yosys to latest 2025-05-15 14:44:26 -07:00
KrystalDelusion 4c72b0ecd8
Merge pull request #5116 from YosysHQ/krys/update_fst 
Update fstlib
 2025-05-16 09:22:52 +12:00
KrystalDelusion f7888c607b
Merge pull request #5089 from YosysHQ/krys/cutpoint_whole 
cutpoint: Re-add whole module optimization
 2025-05-16 09:22:28 +12:00
Krystine Sherwin d0b9a0cb98
sim.cc: Move cycle check 
Calling `throw dst_end_of_data_exception()` when the desired number of cycles has been reached means that the fst reader can't tidy up after itself and leads to memory leaks.
This doesn't happen when the `-stop` flag is used because the `Yosys::FstData` struct tracks the end time and skips the outer callback if the simulation has gone past the desired end time.
Move cycle checking into the inner callback along with the time checking means that the outer callback no longer needs to throw an exception in order to stop checking further values, while still allowing the fst reader to finish reading and deallocate memory.
 2025-05-12 12:48:01 +12:00
Krystine Sherwin cc402ee065
libs/fst: Update upstream 
libfst is no longer included in gtkwave and instead has its own repo.  There has also been some refactoring, so the patches need to update to match, as does sim.cc.
 2025-05-12 10:21:06 +12:00
Akash Levy aeed1ddb74 Update from upstream 2025-05-11 15:16:52 -07:00
Emil J. Tywoniak 90a2c92370 driver: allow --no-version still write things like Generated by Yosys 2025-05-07 11:34:23 +02:00
Krystine Sherwin 7c89355b70
cutpoint: Re-add whole module optimization 
Also add a test script for it.
 2025-05-06 09:57:34 +12:00
Emil J. Tywoniak d7affb8821 driver: add --no-version to suppress writing Yosys version in command outputs 2025-05-05 13:12:08 +02:00
Akash Levy 618cf9d372
Merge branch 'YosysHQ:main' into main 2025-04-28 13:57:29 -07:00
Akash Levy 5f5ed1b29e Merge upstream yosys 2025-04-21 17:36:24 -07:00
Jannis Harder 31d6d0ac17 formalff: Fix -declockgate test and missing emit for memories 2025-04-18 18:57:59 +02:00
Jannis Harder b982da9f6a formalff: Document -declockgate option 2025-04-18 17:44:39 +02:00
Jannis Harder bd154a7188 formalff: Add -declockgate option 2025-04-18 17:44:34 +02:00
Akash Levy e241c9d513
Merge branch 'YosysHQ:main' into main 2025-04-10 14:28:10 -07:00
Krystine Sherwin 87d3b09988
cutpoint.cc: Fold -instances into -blackbox 
Replace `cutpoint -blackbox` behaviour with `cutpoint -blackbox -instances` behaviour.
Drop `-instances` flag.
Add `-noscopeinfo` flag.
Use `RTLIL::Selection::boxed_module()` helper to shortcut blackbox check.
Update `cutpoint_blackbox.ys` tests to match.
 2025-04-11 04:12:35 +12:00
Krystine Sherwin 8b1cc6e05e
cutpoint: Use new selection helpers 2025-04-11 04:12:34 +12:00
Krystine Sherwin b705c546ea
cutpoint: Add -blackbox -instances 
Replace module instances instead of module contents.

This fixes parametrisable width mismatch with read_verilog frontend, but not verific frontend.
 2025-04-11 04:12:34 +12:00
Krystine Sherwin ca57df8927
cutpoint: Add $scopeinfo cell 
Also adds "blackbox" as a valid TYPE.
 2025-04-11 04:12:34 +12:00
Krystine Sherwin 583771ef5b
cutpoint: Add -blackbox option 
Replace the contents of all blackboxes in the design with a formal cut point.
Includes test script.
 2025-04-11 04:12:34 +12:00
Krystine Sherwin cd3b914132
Reinstate #4768 
Revert the reversion so that we can fix the bugs that the PR missed.
 2025-04-08 11:58:05 +12:00
Akash Levy 06c614a010
Merge branch 'YosysHQ:main' into main 2025-04-07 07:28:06 -07:00
Miodrag Milanović d49364d96f
Revert "Refactor full_selection" 2025-04-07 12:11:55 +02:00
Akash Levy 0dab4308a3 Actual merge here 2025-04-06 18:53:43 -07:00
KrystalDelusion 98d4355b82
Merge pull request #4768 from YosysHQ/krys/refactor_selections 
Refactor full_selection
 2025-04-05 14:15:27 +13:00
Akash Levy f218b5ba58 Revert "Represent memory size with size_t" 
This reverts commit bb5f8415af.
 2025-04-04 03:20:07 -07:00
Akash Levy bb5f8415af Represent memory size with size_t 2025-04-04 02:04:34 -07:00
Akash Levy 3d13f7aae2 Bump to latest 2025-03-26 14:56:10 -07:00
Emil J ea74ad33a5
Merge pull request #4961 from YosysHQ/emil/cutpoint-typo 
cutpoint: fix typo
 2025-03-25 21:30:29 +01:00
Emil J. Tywoniak 4991ed9d4b cutpoint: fix typo 2025-03-25 18:10:47 +01:00
Akash Levy 95f489beec Merge nice gzip refactor 2025-03-20 16:47:12 -07:00
Emil J. Tywoniak 4f3fdc8457 io: refactor string and file work into new unit 2025-03-19 13:43:42 +01:00
Krystine Sherwin a3968d43f0
Drop deprecation on Design::selected_modules() 
Instead, change the default `Design::selected_modules()` to match the behaviour (i.e. `selected_unboxed_modules_warn()`) because it's a lot of files to touch and they don't really _need_ to be updated.
Also change `Design::selected_whole_modules()` users over to `Design::selected_unboxed_whole_modules()`, except `attrmap` because I'm not convinced it should be ignoring boxes.  So instead, leave the deprecation warning for that one use and come back to the pass another time.
 2025-03-14 14:08:56 +13:00
Krystine Sherwin dac2bb7d4d
Use selection helpers 
Catch more uses of selection constructor without assigning a design.
 2025-03-14 14:08:13 +13:00
Akash Levy 57bf3a6f51
Merge branch 'YosysHQ:main' into main 2025-01-14 08:38:59 -08:00
Emil J. Tywoniak a58481e9b7 mark all hash_into methods nodiscard 2025-01-14 12:39:15 +01:00
Akash Levy 1dcf75d175 Sync 2024-12-19 21:40:30 -08:00
Emil J. Tywoniak b9b9515bb0 hashlib: hash_eat -> hash_into 2024-12-18 15:09:25 +01:00
Emil J. Tywoniak 4e29ec1854 hashlib: acc -> eat 2024-12-18 15:09:25 +01:00
Emil J. Tywoniak d071489ab1 hashlib: redo interface for flexibility 2024-12-18 14:49:25 +01:00
Alain Dargelas 88ff296657 Activity info and rename cmd 2024-12-11 11:04:35 -08:00
Akash Levy 2c5811daa1 Fix warnings 2024-12-09 11:45:09 -08:00
Alain Dargelas fe684f5fd2 Precision fix 2024-12-03 09:35:11 -08:00
Alain Dargelas f65d98a00d Simulation information for macro power 2024-12-02 20:15:53 -08:00
Akash Levy ea76abdaee Merge 2024-11-11 11:47:58 -08:00
Martin Povišer 1b1a6c4aed
Merge pull request #4525 from georgerennie/peepopt_clock_gate 
peepopt: Add formal opt to rewrite latches to ffs in clock gates
 2024-11-11 14:49:09 +01:00
Alain Dargelas 5be70f436f Added stdout flush and statistical info for debug 2024-11-05 10:21:26 -08:00
Alain Dargelas 44fedf8186 Code cleanup 2024-10-23 09:33:06 -07:00
Alain Dargelas 2c506bfc1b Corrected activity and duty 2024-10-22 16:26:49 -07:00
Alain Dargelas c2aa611e5d Fix comments and add freq annotation in sim pass 2024-10-21 15:53:48 -07:00