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698 Commits

Author SHA1 Message Date
Alain Dargelas 97928493e5 Fix assert 2025-01-14 11:57:03 -08:00
Alain Dargelas d13c70c3c8 Wire rename 2025-01-14 10:03:54 -08:00
Alain Dargelas 14cfd027b7 opt_balance_tree pass formal equiv 2025-01-14 09:35:43 -08:00
Akash Levy 5c514e00a4 Sync with upstream 2025-01-13 17:20:59 -08:00
Akash Levy 941d78a6ac Make splitnetlist more efficient, no preliminary opt_clean in submod, remove $buf cells in opt_clean 2025-01-10 17:12:15 -08:00
Alain Dargelas 0f9901f128 forgot to recompute chains 2025-01-10 14:51:21 -08:00
Alain Dargelas 2ae521bbd1 Built-in splitfanout in muxpack 2025-01-10 13:55:23 -08:00
Alain Dargelas 99afdfa2bf Merge branch 'main' into make_excl 2025-01-10 13:50:59 -08:00
Martin Povišer ca0ace66bc
Merge pull request #4817 from povik/macc_v2-1 
macc: Stop using the B port
 2025-01-08 14:42:51 +01:00
Martin Povišer 366e3f22fb
Merge pull request #4836 from YosysHQ/emil/share-fix-log 
share: fix misleading 0 cells log message
 2025-01-08 13:14:34 +01:00
Martin Povišer 652a1b9806 macc: Stop using the B port 
The B port is for single-bit summands. These can just as well be
represented as an additional summand on the A port (which supports
summands of arbitrary width). An upcoming `$macc_v2` cell won't be
special-casing single-bit summands in any way.

In preparation, make the following changes:

 * remove the `bit_ports` field from the `Macc` helper (instead add any
   single-bit summands to `ports` next to other summands)

 * leave `B` empty on cells emitted from `Macc::to_cell`
 2025-01-08 13:03:35 +01:00
Emil J. Tywoniak 1836a571c9 share: fix misleading log message 2025-01-07 19:25:15 +01:00
Akash Levy 443613da69
Merge branch 'YosysHQ:main' into main 2025-01-07 00:56:19 -05:00
Martin Povišer be351886a5 wreduce: Adjust naming and comments 2025-01-03 12:54:34 +01:00
Alain Dargelas fad1b285df format 2024-12-30 17:25:06 -08:00
Alain Dargelas 0d5d7809f8 format 2024-12-30 17:24:06 -08:00
Alain Dargelas 11c9331a51 format 2024-12-30 17:23:00 -08:00
Alain Dargelas 163b1653b1 format 2024-12-30 17:17:47 -08:00
Alain Dargelas af248c3cb2 format 2024-12-30 17:16:47 -08:00
Alain Dargelas a32a7b27bc format 2024-12-30 17:13:00 -08:00
Alain Dargelas ad80b5336d format 2024-12-30 17:08:07 -08:00
Alain Dargelas 8d6a542a5d Decode logic for muxpack 2024-12-27 15:23:25 -08:00
Alain Dargelas ab0058a568 New -limit_fanout option for opt_balance_tree 2024-12-19 11:44:39 -08:00
Akash Levy 27d3f41ea6 Keep track of new cells in opt_dff and don't rename if only one cell is sliced 2024-12-17 14:18:51 -08:00
Akash Levy 2d105fc2c3 Small naming fixes to remove sig_ prefix 2024-12-17 10:48:28 -08:00
Martin Povišer 08778917db wreduce: Optimize signedness when possible 2024-12-16 12:57:08 +01:00
Akash Levy bfc4ab9138 Fix unordered increment 2024-12-13 13:32:44 -08:00
Alain Dargelas 41c6b71bcb opt_balance_tree allow_off_chain 2024-12-12 09:50:53 -08:00
Akash Levy 2c5811daa1 Fix warnings 2024-12-09 11:45:09 -08:00
Akash Levy f855b39dbb
Merge branch 'YosysHQ:main' into main 2024-11-21 00:34:49 -08:00
Emil J cc17d5bb70
Merge pull request #4612 from georgerennie/george/opt_demorgan_zero_width 
opt_demorgan: skip zero width cells
 2024-11-20 13:33:16 +01:00
Emil J 18459b4b09
Merge pull request #4614 from georgerennie/george/opt_reduce_cell_width 
opt_reduce: keep at least one input to $reduce_or/and cells
 2024-11-20 13:33:04 +01:00
Akash Levy 80169758b6 Another naming improvement 2024-11-12 11:54:15 -08:00
Akash Levy 9f9bacc029 Fixes 2024-11-12 03:44:22 -08:00
Akash Levy a3b4789934 Smallfixes 2024-11-12 02:32:03 -08:00
Akash Levy 0a87b0f075 Smallfix to opt_expr 2024-11-12 01:22:12 -08:00
Akash Levy ddbad572dc Reduce fanout limit to 256 2024-11-11 17:17:25 -08:00
Akash Levy 5e364599be Keep shorter name for opt_merge always 2024-11-11 17:07:41 -08:00
Akash Levy 3da6e3f060 No arguments for opt_balance_tree any more 2024-11-11 17:07:30 -08:00
Akash Levy 894c9816d3 Improve naming: big fix 2024-11-11 17:06:11 -08:00
Akash Levy 4eb820a7ec Update opt_balance_tree to separate the splitfanout 2024-10-31 16:36:17 -07:00
Akash Levy b4d7812662 Add abc, some techmap passes, make opt_balance_tree only balance add/mul 2024-10-30 00:38:05 -07:00
Akash Levy 6401027ff6 Add pmux2shiftx 2024-10-29 15:00:00 -07:00
Akash Levy 751f463994 Add fanout limit 2024-10-25 19:55:57 -07:00
Akash Levy 2523b5d194 Add xnor processing to opt_balance_tree -splitfanout 2024-10-25 02:07:26 -07:00
Akash Levy 469f5a707a
Merge branch 'YosysHQ:main' into main 2024-10-14 11:21:54 -07:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Akash Levy dd487ca8a1 Updating Yosys 2024-10-03 01:46:09 -07:00
Akash Levy 03f76bbddd Remove comments 2024-10-02 16:59:01 -07:00
Akash Levy dd7e302aaa Revert wreduce 2024-10-02 03:55:19 -07:00