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16,053 Commits 122 Branches 61 Tags 50 MiB
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19 Commits

Author SHA1 Message Date
Lofty a119711aac analogdevices: LUT RAM only on positive edge 2025-10-18 12:11:18 +01:00
Lofty f1579304a6 analogdevices: DSP tweaks 2025-10-18 12:10:50 +01:00
Lofty 059925a56a analogdevices: DSP inference 2025-10-16 23:33:59 +01:00
Lofty aab52403f1 analogdevices: remove cells_xtra 2025-10-16 09:27:15 +01:00
Lofty d43f6f7274 analogdevices: timings for t40lp 2025-10-16 08:43:08 +01:00
Lofty 6d0c2fe048 analogdevices: use single tech param 2025-10-16 08:43:08 +01:00
Lofty 7e894d4159 analogdevices: expreso does not care about clock buffers 2025-10-16 08:43:08 +01:00
Lofty 9cfa5fb369 analogdevices: prepare for t40lp timings 2025-10-16 08:43:08 +01:00
Krystine Sherwin 151f530677 analogdevices: Adding RBRAM2 and -tech 2025-10-16 08:43:08 +01:00
Krystine Sherwin edeb6128ab analogdevices: (some) Native BRAM 
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
 2025-10-16 08:43:08 +01:00
Krystine Sherwin 18a4e44b28 analogdevices: Native LUTRAM primitives 2025-10-16 08:43:08 +01:00
Lofty b3e3614c96 analogdevices: LUTRAM config 2025-10-16 08:43:08 +01:00
Lofty 0bec90930f analogdevices: update timing model 2025-10-16 08:43:08 +01:00
Lofty b8254b96c7 analogdevices: user retargeting 2025-10-16 08:43:08 +01:00
Lofty 799a4e4291 analogdevices: more housekeeping 2025-10-16 08:43:08 +01:00
Lofty c7580131ad analogdevices: remove some extra cells! 2025-10-16 08:43:08 +01:00
Lofty 2cdd97a8d4 test suite 2025-10-16 08:43:08 +01:00
Lofty 04fd4d4601 synth_analogdevices: remove scopeinfo cells 2025-10-16 08:43:08 +01:00
Lofty 7878a7e2bd Create synth_analogdevices 2025-10-16 08:43:08 +01:00