yosys

Commit Graph

Author	SHA1	Message	Date
Miodrag Milanovic	1b403b82d7	Handle setting environment on Windows	2024-12-06 11:25:45 +01:00
N. Engelhardt	8b0f665cc5	add setenv pass	2024-12-06 11:25:43 +01:00
Martin Povišer	f3f8037328	abc9_ops: Allow no arcs on box w/o inputs or w/o outputs	2024-12-05 18:32:41 +01:00
Martin Povišer	481d596c43	abc9_ops -prep_box: Adjust for repeated invocation `abc9_ops -prep_box` command interprets the `abc9_box` attribute and prepares a .box file for ABC consumption. Previously this command was removing the attribute as it was processing each module which prevented repeated invocation of this command unless the box definitions were refreshed from a source file. Also the command was keeping existing `abc9_box_id` attributes instead of overwriting them with values from a new number sequence. Change both behaviors to allow repeated invocations of the command on the same design.	2024-12-05 18:32:41 +01:00
Martin Povišer	f4f65493a1	portarcs: Fix confusing disconnected and zero-delay case	2024-12-05 18:27:44 +01:00
Martin Povišer	2c66557d22	portarcs: Fix for case of unused gates	2024-12-05 18:27:43 +01:00
Martin Povišer	d57d21e566	wrapcell: Optionally track unused outputs	2024-12-05 18:16:53 +01:00
KrystalDelusion	c96d02b204	Merge pull request #4784 from YosysHQ/krys/reduce_warnings Reduce number of warnings	2024-12-05 09:16:06 +13:00
Martin Povišer	59a96470df	Merge pull request #4773 from povik/wrapcell wrapcell: Add new command	2024-12-04 11:49:51 +01:00
Martin Povišer	14ee5ce800	Merge pull request #4787 from povik/booth-macc booth: Map simple `$macc` instances too	2024-12-04 11:49:34 +01:00
Emil J	3b8e8ee012	Merge pull request #4797 from YosysHQ/emil/multiple-liberty Allow multiple -liberty args in dfflibmap and clockgate	2024-12-04 11:18:52 +01:00
Martin Povišer	384c191192	Merge pull request #4775 from povik/dont_map techmap: Add `-dont_map` for selective disabling of rules	2024-12-03 20:21:47 +01:00
Martin Povišer	1c7bb700c9	techmap: Rephrase help	2024-12-03 20:20:00 +01:00
Emil J. Tywoniak	6edf9c86cb	libparse: add LibertyMergedCells, enable multiple -liberty args for dfflibmap and clockgate	2024-12-03 17:36:00 +01:00
Emil J. Tywoniak	60fb241cb3	clockgate: clean up argument parsing	2024-12-03 17:35:10 +01:00
Martin Povišer	109d97bb40	Merge pull request #4706 from povik/keep_hierarchy-adjustalgo Adjust `keep_hierarchy` behavior	2024-12-03 12:18:28 +01:00
Martin Povišer	6ad4918121	Account for pre-existing `keep_hierarchy` in cost sum	2024-12-03 11:11:59 +01:00
Martin Povišer	c33f7b92f7	Fix typo	2024-12-03 11:11:02 +01:00
KrystalDelusion	889894a6d2	Merge pull request #4790 from YosysHQ/emil/clockgate-warnings clockgate: reduce build warnings	2024-12-03 13:25:52 +13:00
Lofty	fd05f73d50	dfflibmap: demote some warnings to debug	2024-12-02 14:17:51 +00:00
Emil J. Tywoniak	6b006e5f61	clockgate: reduce build warnings	2024-12-02 10:07:01 +01:00
Martin Povišer	1ded817beb	booth: Map simple `$macc` instances too	2024-12-01 16:00:04 +01:00
Krystine Sherwin	1de5d98ae2	Reduce comparisons of size_t and int `Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`. For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.	2024-11-29 12:53:29 +13:00
Martin Povišer	956313efe8	Merge pull request #4742 from YosysHQ/hierarchy_notify_top_attr Print a note about finding attribute (* top *) in hierarchy	2024-11-28 00:07:18 +01:00
Martin Povišer	2962f8fa88	techmap: Add `-dont_map` for selective disabling of rules	2024-11-27 15:54:37 +01:00
Martin Povišer	79e9258a31	wrapcell: Add new command	2024-11-27 14:01:00 +01:00
Emil J	5b6baa3ef1	Merge pull request #4744 from YosysHQ/emil/clockgate-liberty clockgate: add -liberty	2024-11-20 15:04:00 +01:00
Emil J	56b80bdd22	Merge pull request #4448 from georgerennie/shiftadd_gating peepopt shiftadd: Only match for sufficiently small constant widths	2024-11-20 13:34:09 +01:00
Emil J	cc17d5bb70	Merge pull request #4612 from georgerennie/george/opt_demorgan_zero_width opt_demorgan: skip zero width cells	2024-11-20 13:33:16 +01:00
Emil J	18459b4b09	Merge pull request #4614 from georgerennie/george/opt_reduce_cell_width opt_reduce: keep at least one input to $reduce_or/and cells	2024-11-20 13:33:04 +01:00
Martin Povišer	7ebe451f9a	Merge pull request #4714 from georgerennie/george/proc_dff_bug_multiple_sigs proc_dff: fix early return bug	2024-11-20 13:26:32 +01:00
Emil J. Tywoniak	4d96cbec75	clockgate: reduce errors to warnings	2024-11-18 18:32:18 +01:00
Emil J. Tywoniak	983c54c75f	clockgate: help string add -dont_use and -liberty	2024-11-18 13:57:49 +01:00
Emil J. Tywoniak	a5bc36f77e	clockgate: add -dont_use	2024-11-18 13:45:30 +01:00
Emil J. Tywoniak	e6793da9a0	clockgate: refactor	2024-11-18 12:50:25 +01:00
Emil J. Tywoniak	45880ea7f2	clockgate: add -liberty	2024-11-14 20:37:59 +01:00
Lofty	d9ef388fcc	Merge pull request #4698 from YosysHQ/lofty/dfflibmap-enable dfflibmap: enable inference	2024-11-13 17:50:17 +00:00
Lofty	4f40187759	dfflibmap: move expression code into libparse	2024-11-13 16:06:57 +00:00
Lofty	08ed2c765e	dfflibmap: enable inference	2024-11-13 15:57:45 +00:00
Martin Povišer	2dba345049	portarcs: New command to derive propagation arcs	2024-11-13 16:20:35 +01:00
Martin Povišer	4ce8c7a0d3	Merge pull request #4709 from YosysHQ/emil/idstring-in-fold functional, glift: use fold overload of IdString::in instead of pool …	2024-11-13 15:17:33 +01:00
Martin Povišer	9da7341003	Merge pull request #4727 from georgerennie/george/bufnorm_constants2 bufnorm: preserve constant bits when mapping back to connections	2024-11-13 14:32:15 +01:00
N. Engelhardt	96c526d1ba	Print a note about finding attribute (* top *) in hierarchy	2024-11-13 10:21:44 +01:00
Martin Povišer	915df16c84	Merge pull request #4728 from YosysHQ/emil/fix-filterlib-roundtrip filterlib: preserve value quotes	2024-11-12 10:54:35 +01:00
Emil J. Tywoniak	49e1597ea4	filterlib: preserve value quotes	2024-11-12 01:21:07 +01:00
George Rennie	ff6c9446c0	bufnorm: preserve constant bits when mapping back to connections	2024-11-12 01:05:15 +01:00
Martin Povišer	1b1a6c4aed	Merge pull request #4525 from georgerennie/peepopt_clock_gate peepopt: Add formal opt to rewrite latches to ffs in clock gates	2024-11-11 14:49:09 +01:00
mszelwiga	8e508f2a2a	Fix setting bits of parameters in setundef pass This commit also adds test that verifies correctness of this change.	2024-11-08 17:03:08 +01:00
George Rennie	8f6058a7d6	bufnorm: preserve constant bits driving wires	2024-11-07 11:48:48 +01:00
George Rennie	626dbbe1e0	proc_dff: fix early return bug * early return caused proc_dff to stop considering rules after seeing one async rule - this is because continue should have been used to continue to procecssing the next rule instead of returning from the function	2024-11-07 00:06:03 +01:00
Emil J. Tywoniak	387a235158	functional, glift: use fold overload of IdString::in instead of pool literals	2024-11-06 12:48:32 +01:00
Martin Povišer	29af057430	Merge pull request #4707 from povik/stat-unused stat: Drop unused field	2024-11-05 09:38:29 +01:00
Martin Povišer	4df3a5d7ec	stat: Drop unused field	2024-11-05 09:37:35 +01:00
Martin Povišer	c8fffce2b5	keep_hierarchy: Update messages	2024-11-05 09:03:01 +01:00
Martin Povišer	cf79630be0	keep_hierarchy: Require size information on blackboxes	2024-11-05 09:02:36 +01:00
Martin Povišer	2425352551	keep_hierarchy: Redo hierarchy traversal for `-min_cost`	2024-11-05 09:02:36 +01:00
Lofty	3250f2b82b	Merge pull request #4700 from povik/select-list-mod Add `select -list-mod`	2024-11-04 15:38:42 +00:00
Martin Povišer	cbe73c9047	cellmatch: Visit whiteboxes for `-derive_luts`	2024-11-04 14:28:46 +01:00
Martin Povišer	c9ed6d8dcf	cellmatch: Rename `-lut_attrs` to `-derive_luts`; document option	2024-11-04 14:28:40 +01:00
Martin Povišer	35a20da512	logger: Adjust print	2024-11-04 13:16:40 +01:00
Martin Povišer	7aa3fdab80	select: Add `-list-mod` option	2024-11-04 13:16:13 +01:00
Lofty	dd7ea0ab6c	qwp: remove	2024-10-25 14:09:58 +01:00
Martin Povišer	9432e972f7	Merge pull request #4626 from povik/select-t-at select: Add new `t:@<name>` syntax	2024-10-16 10:18:05 +02:00
Martin Povišer	09be0351ce	select: Add new `t:@<name>` syntax	2024-10-15 12:22:02 +02:00
Emil J. Tywoniak	785bd44da7	rtlil: represent Const strings as std::string	2024-10-14 06:28:12 +02:00
Martin Povišer	a00137c2f6	Merge pull request #4625 from povik/cellmatch-lut cellmatch: Size the `lut` attribute	2024-10-11 14:08:55 +02:00
KrystalDelusion	0be3b7de51	Merge pull request #4635 from YosysHQ/krys/pr_docs_ci Remove make docs race conditions (and other docs fixes)	2024-10-08 21:39:30 +13:00
Miodrag Milanovic	f079772ade	Add TODO for missing help messages	2024-10-08 08:47:51 +02:00
Martin Povišer	9479d3bd3c	Merge pull request #4637 from YosysHQ/emil/bufnorm-warning bufnorm: avoid warning. NFC	2024-10-07 18:01:42 +02:00
Emil J. Tywoniak	a76bcdc58f	bufnorm: avoid remove warning. NFC	2024-10-07 17:58:48 +02:00
Martin Povišer	74e92d10e8	Merge pull request #4593 from povik/aiger2 New aiger backend	2024-10-07 16:11:25 +02:00
Martin Povišer	2e587c835f	abc9_exe: Document SC mapping options	2024-10-07 12:03:49 +02:00
Martin Povišer	3b6dcc7bd0	abc9_exe: Remove `-genlib` option	2024-10-07 12:03:49 +02:00
Martin Povišer	e0a86d5483	abc_new: Start new command for aiger2-based round trip	2024-10-07 12:03:49 +02:00
Martin Povišer	e58a9b6ab6	abc9: Understand ASIC options similar to `abc`	2024-10-07 12:03:48 +02:00
Martin Povišer	ec42b42bd9	cellmatch: Size the `lut` attribute	2024-10-02 11:29:54 +02:00
Mike A.	95a2099c90	Allow whitespace in `tee` command paths	2024-09-29 17:15:59 +02:00
George Rennie	023f029dcf	opt_reduce: keep at least one input to $reduce_or/and cells	2024-09-25 16:21:19 +01:00
George Rennie	58af70624f	opt_demorgan: skip zero width cells	2024-09-24 14:24:59 +01:00
N. Engelhardt	8e1e2b9a39	Merge pull request #4495 from povik/check-avert-costly-detail	2024-09-23 15:19:48 +02:00
Martin Povišer	38de01807e	Mark `bufnorm` experimental	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	80119386c0	Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	8bb70bac8d	Improvements in "bufnorm" pass Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	d027ead4b5	Improvements in "bufnorm" pass Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	f4b7ea5fb3	Improvements in "bufnorm" pass Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	32808a0393	Improvements and fixes to "bufnorm" cmd Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	d0b5dfa6ef	Add bufnorm pass Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Emil J	52382c6544	Merge pull request #4583 from YosysHQ/emil/clock_gate clockgate: centralize clock enables out of FFs	2024-09-16 15:41:01 +02:00
Emil J. Tywoniak	f193bcf683	clockgate: help string	2024-09-16 14:20:33 +02:00
Emil J. Tywoniak	be7c93ec6d	clockgate: 1-bit const 0	2024-09-16 13:58:27 +02:00
Emil J	a8a92d3469	clockgate: help string Co-authored-by: Martin Povišer <povik@cutebit.org>	2024-09-16 13:55:53 +02:00
N. Engelhardt	c8b42b7d48	Merge pull request #4538 from RCoeurjoly/verific_bounds	2024-09-12 13:04:04 +02:00
Emil J. Tywoniak	1e999a3cb7	clockgate: EN can be a bit on a multi-bit wire	2024-09-11 19:18:25 +02:00
Martin Povišer	34572708d5	Merge pull request #4595 from YosysHQ/emil/internal_stats-astnode internal_stats: astnode (sizeof)	2024-09-11 12:21:29 +02:00
Emil J. Tywoniak	1372c47036	internal_stats: astnode (sizeof)	2024-09-11 11:34:20 +02:00
Emil J. Tywoniak	8b464341c2	clockgate: no initvals	2024-09-11 10:24:48 +02:00
Roland Coeurjoly	bdc43c6592	Add left and right bound properties to wire. Add test. Fix printing for signed attributes Co-authored-by: N. Engelhardt <nak@yosyshq.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>	2024-09-10 12:52:42 +02:00
Emil J. Tywoniak	7e473299bd	clockgate: bail on constant signals	2024-09-09 21:20:19 +02:00
Emil J. Tywoniak	e64fceef70	clockgate: prototype clock gating	2024-09-09 15:00:54 +02:00
Hoa Nguyen	c1205ebc42	Initialize area stats in stat pass Currently, the area variables in the stat struct are not initialized. This caused the area stats occasionally being an erroneous value. Signed-off-by: Hoa Nguyen <hnpl@google.com>	2024-09-07 21:30:58 -07:00
Miodrag Milanović	b20df72e1e	Merge pull request #4536 from YosysHQ/functional Functional Backend	2024-09-06 10:05:04 +02:00
Emil J. Tywoniak	14b9155492	internal_stats: fix doc build by adding a help string	2024-09-05 11:22:21 +02:00
Martin Povišer	68fbca8769	Merge pull request #4554 from YosysHQ/emil/devstat internal_stats: init, report current memory consumption on linux and mac	2024-09-03 21:06:46 +02:00
Emil J. Tywoniak	0ce7631956	internal_stats: init, report current memory consumption on linux and mac	2024-09-03 19:28:24 +02:00
George Rennie	bdb5d45591	proc_dff: respect sync rule priorities when generating complex dffsrs * This fixes #4560, where previously the order that sync rules were processed in depended on the order they were pulled out of a std::map. This PR changes this to process them in the order they are found in, respecting the priorities among the async signals	2024-08-28 15:48:07 +01:00
N. Engelhardt	0fc5812dcd	Merge pull request #4541 from YosysHQ/krys/compiler-warnings Resolve (some) compiler warnings	2024-08-26 15:04:16 +02:00
Emily Schmidt	850b3a6c29	convert class FunctionalIR to a namespace Functional, rename functionalir.h to functional.h, rename functional.h to compute_graph.h	2024-08-21 11:04:08 +01:00
Emily Schmidt	8c0f625c3a	functional backend: topological sort starts with the output and next states nodes, other nodes get deleted	2024-08-21 11:03:29 +01:00
Emily Schmidt	bdb59ffc8e	add -fst-noinit flag to sim for not initializing the state from the fst file	2024-08-21 11:03:29 +01:00
Emily Schmidt	dd5ec84a26	fix bugs in drivertools	2024-08-21 11:01:09 +01:00
Jannis Harder	d4e3daa9d0	ComputeGraph datatype for the upcoming functional backend	2024-08-21 11:01:09 +01:00
Jannis Harder	68c3a47945	WIP temporary drivertools example	2024-08-21 11:01:08 +01:00
Emil J	e0d3bbf3c3	Merge pull request #4452 from phsauter/shiftadd-underflow-fix peepopt: avoid shift-amount underflow	2024-08-19 15:45:46 +02:00
Krystine Sherwin	7b47f645d7	Address warnings - Setting default values - Fixing mismatched types - Guarding unused var	2024-08-16 04:30:31 +12:00
Martin Povišer	3057c13a66	Improve libparse encapsulation	2024-08-13 18:47:36 +02:00
Martin Povišer	78382eaa6f	libparse: Adjust whitespace	2024-08-13 18:47:36 +02:00
Martin Povišer	4c3203866f	exec: Add missing newline	2024-08-07 13:02:00 +02:00
George Rennie	236c69bed4	clk2fflogic: run peepopt -formalclk before processing design * this attempts to rewrite clock gating patterns into a form that is less likely to introduce combinational loops with clk2fflogic * can be disabled with -nopeepopt which is useful for testing clk2fflogic	2024-08-07 10:14:04 +01:00
George Rennie	2cb3b6e9b8	peepopt: add formal only peepopt to rewrite latches to ffs in clock gates * this is gated behind the -formalclk flag, which also disables the other synthesis focused optimizations	2024-08-07 10:01:45 +01:00
Miodrag Milanovic	6d98418f3d	Set ranges on exported wires in VCD and FST	2024-08-02 15:23:00 +02:00
Emil J	92cac63845	Merge pull request #4344 from widlarizer/emil/keep_hierarchy cost: add keep_hierarchy pass with min_cost argument	2024-07-29 16:33:08 +02:00
N. Engelhardt	9f869b265c	Merge pull request #4474 from tony-min-1/mchp Add PolarFire FPGA support	2024-07-29 15:28:44 +02:00
Emil J. Tywoniak	4b29f64142	cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter	2024-07-29 10:26:02 +02:00
N. Engelhardt	dd3637f9f0	Merge pull request #4506 from povik/synthprop-formatting synthprop: Reformat the help	2024-07-26 12:28:09 +02:00
Martin Povišer	7ee685a0b0	proc_rom: Set `src` on the emitted memory	2024-07-25 23:14:27 +01:00
Martin Povišer	e063b96104	synthprop: Reformat the help	2024-07-25 11:43:58 +02:00
Martin Povišer	0cefe8a1e8	check: Skip detailed edge modeling if costly	2024-07-18 13:08:19 +02:00
Martin Povišer	e70b1251ad	check: Adjust prints	2024-07-18 13:08:19 +02:00
Martin Povišer	3f71bc469d	check: Rephrase comment	2024-07-18 13:08:19 +02:00
Emil J	1166238c0f	Merge pull request #4176 from povik/opt_expr-performance Improve `opt_expr` performance	2024-07-15 16:10:25 +02:00
Emil J. Tywoniak	532188f239	opt_expr: change info message	2024-07-15 11:14:47 +02:00
Tony Min	d41688f7d7	Revisions (#4 ) * area should be 1 for all LUTs * clean up macros * add log_assert to fail noisily when encountering oddly configured DFF * clean help msg * flatten set to true by default * update * merge mult tests * remove redundant test * move all dsp tests to single file and remove redundant tests * update ram tests * add more dff tests * fix c++20 compile errors * add option to dump verilog * default to use abc9 * remove -abc9 option since its the default now --------- Co-authored-by: tony <minchunlin@gmail.com>	2024-07-08 10:57:16 -04:00
N. Engelhardt	dac5bd1983	Merge pull request #4455 from phsauter/shiftadd-limit-padding peepopt: limit padding from shiftadd	2024-07-06 08:10:25 +02:00
C77874	d0cd01adfe	fixed typos, build with makefile succeeds	2024-07-04 09:33:58 -07:00
C77874	0bb7d1373f	changes made to filenames + references	2024-07-04 08:53:41 -07:00
Chun Lin Min	e5bdc9b5c9	remove DSP48 references	2024-07-03 07:20:29 -07:00
Chun Lin Min	2ced2752e9	replace space indent with tab indent	2024-07-02 13:47:18 -07:00
Chun Lin Min	acddc36389	add PolarFire FPGA support	2024-07-02 12:44:30 -07:00
Catherine	580aaa362d	opt_lut_ins: fix name of global object. NFCI	2024-06-28 15:12:36 +00:00
Emil J. Tywoniak	01f332e750	opt_expr: reduce mostly harmless warning to log	2024-06-25 20:18:49 +02:00
Martin Povišer	fa4a2b6b0d	opt_expr: In clkinv loop ignore irrelevant cells early Each call to `handle_clkpol_celltype_swap` has a conversion of the cell's type ID to an allocated string. This can sum up to a non-negligible time being spent in the clkpol code even for a design which doesn't have any flip-flop gates.	2024-06-24 18:32:33 +02:00
Martin Povišer	7a8a69b65c	opt_expr: Revisit sorting in `replace_const_cells` Avoid building a cell-to-inbit map when sorting the cells, add a warning if we are unable to sort, and move the code treating non-combinational cells ahead of the rest (this means we don't need to pass non-combinational cells to the TopoSort object at all).	2024-06-24 18:32:33 +02:00
Philippe Sauter	2f0f10cb87	peepopt: limit padding from shiftadd The input to a shift operation is padded. This reduced the final number of MUX cells but during techmap it can create huge temporary multiplexers in the log shifter. This significantly increases runtime and resources. A limit is added with a warning when it is used.	2024-06-14 15:33:03 +02:00
Philippe Sauter	74e504330a	peepopt: fix sign check in shiftadd	2024-06-14 13:01:18 +02:00
phsauter	34b5c6d062	peepopt: avoid shift-amount underflow	2024-06-13 23:30:07 +02:00
George Rennie	41aaaa153e	peepopt shiftadd: Only match for sufficiently small constant widths This addresses issue #4445	2024-06-12 14:38:12 +01:00
Miodrag Milanovic	9b82a44d25	Fix help message typo	2024-06-07 08:26:59 +02:00
Martin Povišer	4b67f3757f	Merge pull request #4404 from YosysHQ/povik/bbox_derive box_derive: New command to derive modules for boxes	2024-05-31 19:09:18 +02:00
Martin Povišer	b230c95cc4	select: Adjust help	2024-05-29 20:41:56 +02:00
Martin Povišer	49906be776	select: Introduce `-assert-mod-count`	2024-05-21 16:34:38 +02:00
Martin Povišer	adc1a01490	select: Refactor some flag validation	2024-05-21 16:29:20 +02:00
Martin Povišer	c0a196173a	Rename `bbox_derive` to `box_derive`	2024-05-21 16:18:03 +02:00
N. Engelhardt	e940d248c0	Merge pull request #4326 from povik/logcmd Extend `log` command with `-push`, `-pop`, `-header` options	2024-05-21 15:22:40 +02:00
Martin Povišer	5c929a91c2	bbox_derive: Write help	2024-05-21 14:57:37 +02:00
Martin Povišer	88af059fad	bbox_derive: Fix `done` base type confusion	2024-05-21 14:57:26 +02:00
Emil J. Tywoniak	44b0fdc2bf	bbox_derive: add assert and debug print	2024-05-03 20:43:01 +02:00
Emil J. Tywoniak	e8c58a5528	bbox_derive: fix unininitialized memory UB when run with no named args	2024-05-03 20:41:42 +02:00
Martin Povišer	4c000d3aba	Add new `bbox_derive` command for blackbox derivation	2024-05-03 20:39:11 +02:00
Emil J. Tywoniak	e939182e68	cellmatch: add comments	2024-05-03 16:42:41 +02:00
Martin Povišer	b143e5678f	cellmatch: Rename the special design to `$cellmatch`	2024-05-03 16:42:41 +02:00
Martin Povišer	c0e68dcc4d	cellmatch: Add debug print	2024-05-03 16:42:41 +02:00
Martin Povišer	6a9858cdad	cellmatch: Delegate evaluation to `ConstEval`	2024-05-03 16:42:41 +02:00
Martin Povišer	86e1080f05	cellmatch: New pass	2024-05-03 16:42:41 +02:00
Martin Povišer	6ff4ecb2b4	techmap: Remove `techmap_chtype` from the result	2024-05-03 13:33:28 +02:00
Martin Povišer	fc82251105	techmap: Support dynamic cell types	2024-05-03 13:33:28 +02:00
N. Engelhardt	34d9a7451e	Merge pull request #4333 from YosysHQ/fix_hierarchy_generate fix hierarchy -generate mode handling of cells	2024-04-25 09:56:24 +02:00
KrystalDelusion	c3ae33da33	Merge pull request #4285 from YosysHQ/typo_fixup Typo fixing	2024-04-25 09:54:48 +12:00
Martin Povišer	171577f909	Merge pull request #4340 from gadfort/abc-lib-merge add support for using ABCs library merging when providing multiple liberty files	2024-04-17 22:01:20 +02:00
Jannis Harder	2bd889a59a	formalff -setundef: Fix handling for has_srst FFs The `has_srst`` case was checking `sig_ce` instead of `sig_srst` due to a copy and paste error. This would crash when `has_ce` was false and could incorrectly determine that an initial value is unused when `has_ce` and `has_srst` are both set.	2024-04-15 11:53:30 +02:00
Martin Povišer	b827b9862f	Merge pull request #4265 from povik/iattr_help memory_map: Explain `-iattr` better	2024-04-13 18:13:58 +02:00
Martin Povišer	4a8cdfabbb	Merge pull request #4169 from povik/clean-opt_clean-step2 opt_clean: Remove dead assertion	2024-04-13 18:12:40 +02:00
Peter Gadfort	a48825a604	add support for using ABCs library merging when providing multiple liberty files	2024-04-12 13:57:29 -04:00
N. Engelhardt	b87327d1b9	fix hierarchy -generate mode handling of cells	2024-04-12 13:38:33 +02:00
Emil J	c5912f4f95	Merge pull request #4313 from widlarizer/emil/fix-opt-demorgan-warning opt_demorgan: fix extra args warning	2024-04-10 12:49:14 +02:00
Martin Povišer	b00abe4a26	Extend `log` command with `-push`, `-pop`, `-header` options	2024-04-10 11:49:20 +02:00
Martin Povišer	47931f9050	Merge pull request #4295 from gadfort/add-ports-stat add port statistics to stat command	2024-04-08 11:12:02 +02:00
Emil J. Tywoniak	4bb3b099d2	opt_demorgan: fix extra args warning	2024-04-03 10:02:53 +02:00
N. Engelhardt	c98cdc2a42	Merge pull request #4184 from povik/check-loop-edges Use cell edges data in `check`, improve messages	2024-03-25 16:19:35 +01:00
Peter Gadfort	160e3e089a	add port statistics to stat command	2024-03-22 09:20:20 -04:00
Krystine Sherwin	3eeefd23e3	Typo fixup(s)	2024-03-18 11:09:23 +13:00
N. Engelhardt	e4f11eb0a0	Merge pull request #4228 from povik/synth-inject synth: Introduce `-extra-map` for amending techmap	2024-03-11 14:55:45 +01:00
Martin Povišer	206d894c56	check: Omit private wires in loop report	2024-03-11 10:45:36 +01:00
Martin Povišer	d01728aaa5	celledges: Register async FF paths	2024-03-11 10:45:36 +01:00
Martin Povišer	4fdcf388d3	check: Assert edges data is not out-of-bounds	2024-03-11 10:45:17 +01:00
Martin Povišer	b6112b3551	check: Consider read ports in loop detection	2024-03-11 10:45:17 +01:00
Martin Povišer	fa74d0bd1a	check: Use cell edges data in detecting combinational loops	2024-03-11 10:43:49 +01:00
Martin Povišer	c5ae74af34	check: Improve found loop logging Print the detected loop in-order, and include source location for each node, if available.	2024-03-11 10:43:49 +01:00
N. Engelhardt	d70113a909	Merge pull request #3972 from nakengelhardt/celledges_shift_ops celledges: support shift ops	2024-03-08 09:35:47 +01:00
Martin Povišer	158fbf881e	memory_map: Explain `-iattr` better	2024-03-06 15:15:37 +01:00
Jannis Harder	04ecabdd1f	Merge pull request #4222 from jix/pdr-X write_aiger: Include `$assert` and `$assume` cells in -ywmap output	2024-03-05 15:13:51 +01:00
Zapta	36c244aeda	Merge remote-tracking branch 'upstream'	2024-03-04 14:55:14 -08:00
Jannis Harder	d8cdc213a6	rename -witness: Bug fix and rename formal cells Rename formal cells in addition to witness signals. This is required to reliably track individual property states for the non-smtbmc flows. Also removes a misplced `break` which resulted in only partial witness renaming.	2024-03-04 16:53:03 +01:00
Jannis Harder	16f6386613	Merge pull request #4224 from povik/equiv_simple-fix equiv_simple: Take FFs into account for driver map	2024-03-04 15:53:34 +01:00
Zapta	672c89498a	Added to the Show command a -wireshape <graphviz-shape> flag. This allows to control the shape of wire nodes, for example, -wireshape plaintext. The motivation is to allow the user to reduce visual loads of wires. This does not change the default behavior of using a diamond shape.	2024-03-02 11:20:53 -08:00
N. Engelhardt	6dc5da3ed9	Merge pull request #4232 from povik/mem-ui-fixes opt_mem, memory_*: Refuse to operate in presence of processes	2024-02-26 16:09:27 +01:00
Roland Coeurjoly	4a2fb18718	Changes in libs, passes and tests Makefiles. LDLIBS -> LIBS. LDFLAGS -> LINKFLAGS. CXX is clang++ or g++, not clang and gcc	2024-02-25 17:23:56 +01:00
Roland Coeurjoly	033fa10307	We use CXX instead of LD for linking yosys-filterlib	2024-02-25 16:49:28 +01:00
Martin Povišer	030d639201	opt_mem, memory_*: Refuse to operate in presence of processes Processes can contain `MemWriteAction` entries which are invisible to most passes operating on memories but which will be lowered to write ports later on by `proc_memwr`. For that reason we can get corrupted RTLIL if we sequence the memory passes before `proc`. Address that by making the affected memory passes ignore modules with processes.	2024-02-23 12:27:53 +01:00
Martin Povišer	975517b022	memory_memx: Fix log header	2024-02-23 12:27:10 +01:00
Martin Povišer	53ca7b48f8	techmap: Fix help message wording	2024-02-22 22:00:56 +01:00
Martin Povišer	4c96546717	equiv_simple: Take FFs into account for driver map This fixes an issue introduced in commit `26644ea` due to which flip-flops are inadvertently ignored when building up driver map. The mentioned commit wasn't without functional change after all.	2024-02-21 12:05:52 +01:00
Austin Rovinski	03cadf6474	dfflibmap: use patmatch() from kernel/yosys.cc Replace OS matching functions with yosys kernel function Signed-off-by: Austin Rovinski <rovinski@nyu.edu>	2024-02-20 11:04:55 -05:00
Miodrag Milanović	bc8a3a5b18	Merge pull request #4219 from rovinski/master dfflibmap: Add a -dont_use flag to ignore cells	2024-02-20 12:43:44 +01:00
Miodrag Milanović	a3c81f4d62	Merge pull request #4216 from YosysHQ/show_href show: Add option to add cell/wire "src" attribute into graphviz attribute href	2024-02-19 20:50:53 +01:00
Austin Rovinski	5059bb1d4f	dfflibmap: force PathMatchSpecA on WIN32 Depending on the WIN32 compilation mode, PathMatchSpec may expect a LPCSTR or LPCWSTR argument. char* is only convertable to LPCSTR, so use that implementation Signed-off-by: Austin Rovinski <rovinski@nyu.edu>	2024-02-19 14:40:46 -05:00
Austin Rovinski	689feed012	dfflibmap: Add a -dont_use flag to ignore cells This is an alternative to setting the dont_use property in lib. This brings dfflibmap in parity with the abc pass for dont_use. Signed-off-by: Austin Rovinski <rovinski@nyu.edu>	2024-02-19 13:00:18 -05:00
Martin Povišer	db947e4c71	Merge pull request #4218 from kivikakk/proc_rom-actionless-switch proc_rom: don't assert on big actionless switch.	2024-02-19 16:21:40 +01:00
N. Engelhardt	4b99db0b73	Merge pull request #4177 from povik/connect-extra_args connect: Do interpret selection arguments	2024-02-19 15:18:37 +01:00
N. Engelhardt	aebb7a0c4d	Merge pull request #4188 from povik/dlatch-bwmux proc_dlatch: Include `$bwmux` among considered mux cells	2024-02-19 15:15:03 +01:00
Amelia Cuss	bf4a46ccb3	proc_rom: don't assert on big actionless switch. See the test case. PROC_ROM will consider this for evaluation, even though -- without any actions -- lhs is empty (but still "uniform"). A zero-width memory is constructed, which later fails check with: ERROR: Assert `width != 0' failed in kernel/mem.cc:518. Ensure we don't proceed if there's nothing to encode.	2024-02-18 01:33:28 +11:00
N. Engelhardt	61b3b9b58a	Merge pull request #4197 from QuantamHD/sequential_area stat: Add sequential area output to stat -liberty	2024-02-16 19:15:44 +01:00
Ethan Mahintorabi	b8a1009de9	Update passes/cmds/stat.cc Make reporting line more clear about the non cumulative area of sequential cells Co-authored-by: N. Engelhardt <nakengelhardt@gmail.com>	2024-02-16 07:44:09 -08:00
Ethan Mahintorabi	f0df0e3912	update type and variable names Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>	2024-02-16 00:01:44 +00:00
Ethan Mahintorabi	2d8343d423	update type and variable names Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>	2024-02-15 23:59:19 +00:00
Jannis Harder	bbdfcfdf30	clk2fflogic: Fix handling of $check cells Fixes a bug in the handling of the recently introduced $check cells. Both $check and $print cells in clk2fflogic are handled by the same code and the existing tests for that were only using $print cells. This missed a bug where the additional A signal of $check cells that is not present on $print cells was dropped due to a typo, rendering $check cells non-functional. Also updates the tests to explicitly cover both cell types such that they would have detected the now fixed bug.	2024-02-14 11:42:27 +01:00
Miodrag Milanovic	834276a2f7	show: Add option to add cell/wire "src" attribute into graphviz attribute href	2024-02-14 09:50:53 +01:00
Miodrag Milanović	edb95c69a9	Merge pull request #4084 from jix/scopeinfo $scopeinfo support	2024-02-12 09:51:22 +01:00
Ethan Mahintorabi	8566489d85	stat: Add sequential area output to stat -liberty Checks to see if a cell is of type ff in the liberty, and keeps track of an additional area value. ``` Chip area for module '\addr': 92.280720 Sequential area for module '\addr': 38.814720 ``` Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>	2024-02-09 23:51:00 +00:00
Miodrag Milanović	2f4c917dac	Merge pull request #4181 from povik/ci-cxxstd-fix ci: Fix CXXSTD typo	2024-02-08 18:55:47 +01:00
Martin Povišer	043f1e2bcb	opt_lut: Remove leftover `-dlogic` help	2024-02-08 17:49:44 +01:00
Martin Povišer	af1a5cfeb9	Address `SigBit`/`SigSpec` confusion issues under c++20	2024-02-08 17:48:36 +01:00
Martin Povišer	862f2fd705	proc_dlatch: Include `$bwmux` among considered mux cells	2024-02-08 00:08:50 +01:00
Jannis Harder	bfd9cf63db	Ignore $scopeinfo in opt_merge	2024-02-06 17:51:29 +01:00
Jannis Harder	8902fc94b6	Suport $scopeinfo in flatten and opt_clean	2024-02-06 17:51:29 +01:00
Miodrag Milanović	269c50f90e	Merge pull request #4130 from jix/hierarchy-defer-notop hierarchy: Without a known top module, derive all deferred modules	2024-02-06 12:08:01 +01:00
Jannis Harder	0470cbb00d	hierarchy: Without a known top module, derive all deferred modules This fixes hierarchy when used with cell libraries that were loaded with -defer and also makes more of the hierarchy visible to the auto-top heuristic.	2024-02-06 10:31:40 +01:00
Claire Xen	1b73b5beb7	Merge pull request #4174 from YosysHQ/claire/overwrite Add API to overwrite existing pass from plugin	2024-02-05 23:49:24 +01:00
N. Engelhardt	f96e27ac14	Merge pull request #4123 from povik/clean-opt_clean opt_clean: Add commentary, remove dead code	2024-02-05 15:08:34 +01:00
Catherine	c7bf0e3b8f	Add new `$check` cell to represent assertions with a message.	2024-02-01 20:10:39 +01:00
Jannis Harder	e1a59ba80b	async2sync, clk2fflogic: Add support for $check and $print cells	2024-02-01 20:10:39 +01:00
Jannis Harder	6c4902313b	chformal: Support $check cells and add chformal -lower This adds support for `$check` cells in chformal and adds a `-lower` mode which converts `$check` cells into `$assert` etc. cells with a `$print` cell to output the `$check` message.	2024-02-01 20:10:39 +01:00
Martin Povišer	a84fa0a277	connect: Do interpret selection arguments Instead of silently ignoring what would ordinarily be the selection arguments to a pass, interpret those and mark the support in the help message.	2024-02-01 10:28:36 +01:00
Martin Povišer	6c4bc5aae5	Merge pull request #4165 from phsauter/shiftadd-offset-fix peepopt: handle offset too large in `shiftadd`	2024-01-31 13:47:39 +01:00
Philippe Sauter	cbdf9b2f9c	peepopt: handle empty src-attribute in shiftadd	2024-01-31 13:07:01 +01:00
Claire Xenia Wolf	4fa314c0bd	Add API to overwrite existing pass from plugin Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-01-30 17:51:11 +01:00
Philippe Sauter	7f8b6dd982	peepopt: delete unnecessary comment in shiftadd	2024-01-30 09:51:21 +01:00
Martin Povišer	23c9828d70	opt_clean: Remove dead branch	2024-01-29 11:26:44 +01:00
Martin Povišer	7afc0696e2	opt_clean: Assert an impossible path isn't taken	2024-01-29 11:26:44 +01:00
Martin Povišer	ec065186d3	opt_clean: Add commentary around wire cleaning, NFC	2024-01-29 11:26:44 +01:00
Philippe Sauter	68a9aa7c29	peepopt: handle offset too large in `shiftadd` If the offset is larger than the signal itself, meaning the signal is completely shifted out, it tried to extract a negative amount of bits from the old signal. This RTL pattern is suspicious since it is a complicated way of arriving at a constant value, so we warn the user.	2024-01-26 16:44:30 +01:00
Jannis Harder	7c818d30f7	sim: Bring $print trigger/sampling semantics in line with FFs	2024-01-25 16:21:03 +01:00
Catherine	3d9e44d182	hierarchy: keep display statements, like formal assertions.	2024-01-22 10:09:22 +00:00
Stephen Tong	b3e7390c0e	Fix typo in stat help	2024-01-21 16:32:05 -05:00
N. Engelhardt	e1f4c5c9cb	Merge pull request #4133 from YosysHQ/show_color_proc show: allow setting colors via selection on PROC boxes	2024-01-17 17:56:53 +01:00
Martin Povišer	6a7fad4dd9	Merge pull request #4132 from povik/opt_lut_ice40 opt_lut: Replace `-dlogic` with `-tech ice40`	2024-01-17 14:26:28 +01:00
N. Engelhardt	fb4eeb1344	show: allow setting colors via selection on PROC boxes	2024-01-15 17:47:59 +01:00
Martin Povišer	149bcd88ad	Merge pull request #4026 from uis246/fix-format Fix printf formats	2024-01-15 16:04:11 +01:00
Martin Povišer	568418b50b	opt_lut: Replace `-dlogic` with `-tech ice40`	2024-01-15 12:35:21 +01:00
uis	5902b2826d	Fix printf formats	2024-01-15 12:07:54 +01:00
Dag Lem	acf916f654	Restore sim output from initial $display	2024-01-14 16:52:51 +01:00
Jannis Harder	57b4e16acd	sim: Include $display output in JSON summary This allows tools like SBY to capture the $display output independent from anything else sim might log. Additionally it provides source and hierarchy locations for everything printed.	2024-01-11 12:01:39 +01:00
N. Engelhardt	78541be4d8	Merge pull request #3971 from povik/equiv_simple-fixes Fixes to `equiv_simple`	2023-12-18 16:31:02 +01:00
Jannis Harder	cca12d9d9b	Merge pull request #4055 from povik/sim-hier-prints sim: Print hierarchy for failed assertions	2023-12-11 16:55:36 +01:00
Jannis Harder	7b74caa5db	peepopt: Fix padding for the peepopt_shiftmul_right pattern The previous version could easily generate a large amount of padding when the constant factor was significantly larger than the width of the shift data input. This could lead to huge amounts of logic being generated before then being optimized away at a huge performance and memory cost. Additionally and more critically, when the input width was not a multiple of the constant factor, the input data was padded with 'x bits to such a multiple before interspersing the 'x padding needed to align the selectable windows to power-of-two offsets. Such a final padding would not be correct for shifts besides $shiftx, and the previous version did attempt to remove that final padding at the end so that the native zero/sign/x-extension behavior of the shift cell would be used, but since the last selectable window also got power-of-two padding appended after the padding the code is trying to remove got added, it did not actually fully remove it in some cases. I changed the code to only add 'x padding between selectable windows, leaving the last selectable window unpadded. This omits the need to add final padding to a multiple of the constant factor in the first place. In turn, that means the only 'x bits added are actually impossible to select. As a side effect no padding is added when the constant factor is equal to or larger than the width of the shift data input, also solving the reported performance bug. This fixes #4056	2023-12-06 18:35:44 +01:00
Martin Povišer	6581b5593c	sim: Print hierarchy for failed assertions	2023-12-06 12:09:07 +01:00
Martin Povišer	16ea497d7c	pmgen: Have a single make pattern Remove duplicate %.pmg -> %_pm.h pattern. One of the duplicates overrode the other, and in some conditions there were build races as to whether the target directory for the generated header would exist. Instead have a single rule which is properly generalized.	2023-12-05 18:30:13 +01:00
Martin Povišer	d6566eb344	booth: Redo baseline architecture summation Redo the summation logic: strive for some degree of balance on the generated Wallace tree, emit an `$add` cell for the final summation.	2023-11-22 15:47:11 +01:00
Martin Povišer	beb5cb55a5	booth: Expose `-lowpower` option	2023-11-22 15:29:59 +01:00
Martin Povišer	7005ea9411	booth: Revisit help	2023-11-22 15:29:59 +01:00
Martin Povišer	48b73be8c6	booth: Replace the default signed architecture Generalize what was formerly the unsigned-only architecture to support both signed and unsigned multiplication, use that as default, and set aside the special low-power architecture that was formerly used for signed multipliers.	2023-11-22 15:29:59 +01:00
Martin Povišer	f50894d8bf	booth: Drop extra decoder arguments	2023-11-22 15:29:54 +01:00
Martin Povišer	579f6bdc17	booth: Do not special-case bottom rows Later on all the rows are cropped to the target size anyway, so there's no harm in transitionally including extra top bits.	2023-11-22 15:12:15 +01:00
Martin Povišer	da207cdce0	booth: Make less assumptions when aligning partial products	2023-11-22 15:12:15 +01:00
Martin Povišer	69e994ff75	booth: Clean unused FA index variable	2023-11-22 12:47:09 +01:00
Martin Povišer	d8408b2350	booth: Move up signed quadrant 1 logic	2023-11-22 12:46:15 +01:00
Martin Povišer	8d33cc2fb6	booth: Refactor signed CPA	2023-11-22 12:46:15 +01:00
Martin Povišer	00e899f98d	booth: Refactor signed multiplier full adders emission	2023-11-22 12:46:15 +01:00
N. Engelhardt	63cec22a0c	Merge pull request #3883 from phsauter/peepopt-shiftadd peepopt: Add `shiftadd` pattern	2023-11-07 10:42:15 +01:00
phsauter	3618294bac	peepopt: Add assert of consistent `shiftadd` data	2023-11-06 16:35:00 +01:00
Philippe Sauter	b6df900bcc	peepopt: Describe `shiftadd` rule in help message	2023-11-06 14:01:37 +01:00
phsauter	9ca57d9f13	peepopt: fix and refactor `shiftadd` - moved all selection and filtering logic to the match block - applied less-verbose code suggestions - removed constraint on number of bits in shift-amount - added check for possible wrap-arround in the operation	2023-11-06 14:01:37 +01:00
Philippe Sauter	72c6a01e67	peepopt: Add initial `shiftadd` pattern	2023-11-06 14:01:37 +01:00
N. Engelhardt	080da693d1	memory_libmap: update search order for attributes	2023-10-24 13:55:45 +02:00
N. Engelhardt	1b6d1e9419	memory_libmap: look for ram_style attributes on surrounding signals	2023-10-19 19:23:35 +02:00
Lofty	d21c464ae4	Merge pull request #3946 from rmlarsen/toposort Speed up TopoSort by 2.7-3.3x.	2023-10-17 13:00:18 +01:00
Claire Xen	a4951a3a97	Merge pull request #3986 from povik/sim-ui-fixes Slightly improve `sim` UI	2023-10-16 16:54:05 +02:00
N. Engelhardt	a2f59cf911	Merge pull request #3990 from zeldin/deterministic_scc	2023-10-16 16:51:54 +02:00
Martin Povišer	d6d1cc705e	pmgen: Fix sample syntax	2023-10-16 14:19:15 +02:00
Martin Povišer	660be4a31e	peepopt: Describe rules in help message	2023-10-16 14:19:15 +02:00
Martin Povišer	5c0c8251c3	peepopt: Remove broken `-generate` option	2023-10-16 14:19:10 +02:00
Martin Povišer	aa9b86aeec	peepopt: Add left-shift 'shiftmul' variant Add a separate shiftmul pattern to match on left shifts which implement demuxing. This mirrors the right shift pattern matcher but is probably best kept separate instead of merging the two into a single matcher. In any case the diff of the two matchers should be easily readable.	2023-10-16 13:52:38 +02:00
Martin Povišer	038a5e1ed4	peepopt: Support shift amounts zero-padded from below The `opt_expr` pass running before `peepopt` can interfere with the detection of a shiftmul pattern due to some of the bottom bits of the shift amount being replaced with constant zero. Extend the detection to cover those situations as well.	2023-10-16 13:52:06 +02:00
Martin Povišer	dd1a8ae49a	peepopt: Try to use original wires	2023-10-16 13:52:06 +02:00
Martin Povišer	bd8a81a907	peepopt: Clean up 'shiftmul' a bit No functional change intended.	2023-10-16 13:52:06 +02:00
Martin Povišer	a0c3be3aae	peepopt: Drop unused 'initbits' code Drop code that was once used by the 'dffmux' pattern but now is unused after that pattern has been obsoleted by the 'opt_dff' pass.	2023-10-16 13:52:06 +02:00
N. Engelhardt	6c562c76bc	fix handling right shifts	2023-10-12 11:46:09 +02:00
N. Engelhardt	3e22791810	Merge pull request #3975 from rmlarsen/optmerge	2023-10-09 17:05:19 +02:00
Adrian Parvin Ouano	535ecf84ac	alumacc: merge independent of sign	2023-10-08 01:23:14 +08:00
Adrian Parvin Ouano	74d38db3b5	alumacc: merge eq independent of sign	2023-10-08 01:23:14 +08:00
Marcus Comstedt	0ca39e233b	scc: Use hashlib instead of STL for deterministic behaviour	2023-10-07 10:43:00 +02:00
Rasmus Munk Larsen	0a37c2a301	Fix translation bug: The old code really checks for the presense of a node, not an edge in glift and flatten. Add back statement that inserts nodes in order in opt_expr.cc.	2023-10-05 17:01:42 -07:00
Martin Povišer	c3fd88624a	sim: Bail on processes Instead of silently missimulating, error out when there are processes found in the simulation hierarchy.	2023-10-05 19:25:17 +02:00
Martin Povišer	a782b15aae	sim: s/instanced/instantiated/	2023-10-05 19:25:17 +02:00
Martin Povišer	6ac43e49bc	sim: Change clocked read port suggestion to `memory_nordff` `memory_nordff` has the advantage that it can be called just ahead of the simulation step no matter whether the clocked read port has been inferred or was explicitly instantiated in a flow.	2023-10-05 19:25:17 +02:00
Martin Povišer	0434f9d3d1	booth: Fix vacancy check when summing down result In commit `fedd12261` ("booth: Move away from explicit `Wire` pointers") a bug was introduced when checking for vacant slots in arrays holding some intermediate results. Non-wire SigBit values were taken to imply a vacant slot, but actually a constant one can make its way into those results, if the multiplier cell configuration is just right. Fix the vacancy check to address the bug.	2023-10-04 23:21:40 +02:00
Rasmus Munk Larsen	57a2b4b0cd	Explicitly use uint64_t as the type of fingerprint to avoid type mismatch with some compilers.	2023-10-03 15:02:02 -07:00
Rasmus Munk Larsen	8e0308b5e7	Revert changes to celltypes.h. Use dict instead of std::unordered_map and most hash function for uint64_t to hashlib.h to support this.	2023-10-03 14:25:59 -07:00
Martin Povišer	1f1f43edd9	equiv_simple: Fix seed handling in non-short mode	2023-10-03 13:05:42 +02:00
Martin Povišer	dbf11da50a	equiv_simple: Do not special-case flip-flop types in cone expansion If there's an asynchronous flip-flop type, it will be caught by not having a synchronous SAT model later on. Otherwise we can support all flip-flops.	2023-10-03 13:05:42 +02:00
Martin Povišer	26644ea779	equiv_simple: Drop hollow conditional All the listed flip-flop types would be known cells, so the extra part of the conditional is without effect.	2023-10-03 13:05:42 +02:00
Rasmus Munk Larsen	bce984fa60	Speed up OptMergePass by 1.7x. The main speedup comes from swithing from using a SHA1 hash to std::hash<std::string>. There is no need to use an expensive cryptographic hash for fingerprinting in this context.	2023-10-02 15:57:18 -07:00
Rasmus Munk Larsen	1bbc12f389	Revert changes to techmap.cc.	2023-10-02 17:32:56 +01:00
Rasmus Munk Larsen	67f1700486	Revert formatting changes.	2023-10-02 17:32:56 +01:00
Rasmus Munk Larsen	abd9c51963	Speed up simplemap_map by 11.6x by directly inserting the cell source attribute in the new object's 'attributes' map instead of calling set_attr_pool to create a new pool and then copying that. Based on a suggestion by Martin Poviser in a comment on https://github.com/YosysHQ/yosys/pull/3959	2023-10-02 17:32:56 +01:00
Jannis Harder	8b42abee50	Merge pull request #3961 from jix/dft-fixes	2023-10-02 16:58:15 +02:00
Jannis Harder	ecf09b9271	Merge pull request #3962 from jix/sim-noinitstate	2023-10-02 16:57:46 +02:00
N. Engelhardt	dcb600ab81	Merge pull request #3938 from povik/booth-cleanup	2023-10-02 16:10:17 +02:00
Jannis Harder	5daa49bafb	dft_tag: Fix size extending $x[n]or and $reduce_{or,bool}/$logic_not	2023-09-28 17:33:55 +02:00
Jannis Harder	7eaa4bcb46	sim: Add -noinitstate option and handle non-cosim initstate This adds the -noinitstate option which is required to simulate counterexamples to induction with yw-cosim. Also add handling for $initstate cells for non-co-simulation.	2023-09-28 17:29:24 +02:00
Martin Povišer	6b70b3dbef	booth: Fix assertion Fix assertion to what it should be per Andy's comments.	2023-09-28 11:50:57 +02:00
N. Engelhardt	3319fdc46e	show: use dot for wire aliases instead of BUF	2023-09-25 17:20:16 +02:00
Martin Povišer	91bcf81dbd	booth: Note down debug prints are broken	2023-09-25 14:51:26 +02:00
Martin Povišer	7179e4f4b8	booth: Improve user interface	2023-09-25 14:50:41 +02:00
Martin Povišer	cde2a0b926	booth: Make more use of appropriate helpers Use the `addFa` helper, do not misuse `new_id` and make other changes to the transformation code.	2023-09-25 14:50:41 +02:00
Martin Povišer	62302f601d	booth: Remove more of unused helpers	2023-09-25 14:50:41 +02:00
Martin Povišer	30f8387b75	booth: Rewrite the main cell selection loop	2023-09-25 14:50:41 +02:00
Martin Povišer	986507f95f	booth: Streamline the low-level circuit emission For the basic single-bit operations, opt for gate cells (`$_AND_` etc.) instead of the coarse cells (`$and` etc.). For the emission of cells move to the conventional module methods (`module->addAndGate`) away from the local helpers. While at it, touch on the surrounding code.	2023-09-25 14:50:41 +02:00
Martin Povišer	cb05262fc4	booth: Remove now-unused helpers	2023-09-25 14:50:41 +02:00
Martin Povišer	fedd12261f	booth: Move away from explicit `Wire` pointers To represent intermediate signals use the `SigBit`/`SigSpec` classes as is customary in the Yosys codebase. Do not pass around `Wire` pointers unless we have special reason to.	2023-09-25 14:50:41 +02:00
Rasmus Munk Larsen	9ed38bf9b6	Speed up the autoname pass by 3x. (#3945 ) * Speed up the autoname pass by 2x. This is accomplished by only constructing IdString objects for plain strings that have a higher score. * Defer creating IdStrings even further. This increases the speedup to 3x.	2023-09-21 09:46:49 +00:00
Rasmus Munk Larsen	e0042bdff7	Speed up TopoSort. The main sorting algorithm implementation in TopoSort::sort_worker is 11-12x faster. Overall, the complete sequence of building the graph and sorting is about 2.5-3x faster. The overall impact in e.g. the replace_const_cells optimization pass is a ~25% speedup. End-to-end impact on our synthesis flow is about 3%.	2023-09-20 15:49:05 -07:00
Martin Povišer	54be4aca90	Merge pull request #3924 from andyfox-rushc/master multpass -- create Booth Encoded multipliers for	2023-09-18 16:46:59 +02:00
Jannis Harder	62b4df4989	dft_tag: Implement `$overwrite_tag` and `$original_tag` This does not correctly handle an `$overwrite_tag` on a module output, but since we currently require the user to flatten the design for cross-module dft, this cannot be observed from within the design, only by manually inspecting the signals in the design.	2023-09-13 11:32:36 +02:00
Jannis Harder	46a35da28c	Add `future` pass to resolve `$future_ff` cells	2023-09-13 11:32:36 +02:00
Jannis Harder	7a0c37b62d	Initial dft_tag implementation This is still missing a mode to rewrite $overwrite_tag and $original_tag by injecting $set_tag and $get_tag in the right places. It's also missing bit-precise propagation models for shifts and arithmetic and requires the design to be flattened.	2023-09-13 11:32:36 +02:00
Miodrag Milanović	88ce47e4f0	Merge pull request #3892 from QuantamHD/dont_use abc: Exposes dont_use flag in ABC	2023-09-12 14:58:44 +02:00
andyfox-rushc	e4fe522767	MultPassWorker -> BoothPassWorker	2023-09-11 13:00:11 -07:00
andyfox-rushc	eccc0ae6db	Based passes/techmap/Makefile.inc changes on latest in yosys	2023-09-11 12:14:12 -07:00
andyfox-rushc	a2c8e47295	multpass.cc -> booth.cc, added author/support contact info	2023-09-11 11:39:13 -07:00
Martin Povišer	5bef9b4e75	Merge pull request #3915 from povik/sim-print sim: Add print support	2023-09-11 17:03:59 +02:00
andyfox-rushc	1b5287af59	cpa_carry array added to heap	2023-09-10 14:20:30 -07:00
andyfox-rushc	8d4b6c2f69	Switched arrays for signed multiplier construction to heap	2023-09-10 13:31:47 -07:00
andyfox-rushc	d77fb81507	2d array -> 1d array in module generator	2023-09-10 12:45:36 -07:00
andyfox-rushc	6d29dc659b	renamed passname to booth, replaced connect_sigSpecToWire with connect, updated test script	2023-09-08 15:34:56 -07:00
andyfox-rushc	411acc4a0a	Fixed edge size cases for signed/unsigned booth generator	2023-09-08 13:41:31 -07:00
andyfox-rushc	fedefa26bc	multpass -- create Booth Encoded multipliers for	2023-09-06 16:35:17 -07:00
Jannis Harder	e187fc915e	xprop: Fix polarity errors and generate hdlnames * Fixes a non-deterministic polarity error for $eqx/$nex cells * Fixes a deterministic polarity error for $_NOR_ and $_ORNOT_ cells * Generates hdlnames when xprop is run after flatten	2023-09-06 19:25:47 +02:00
Martin Povišer	d4d951657f	sim: Add `-assert` option to fail on failed assertions	2023-09-05 10:46:04 +02:00
Martin Povišer	e995dddeaa	abc: Warn about replacing undef bits	2023-09-05 10:45:30 +02:00
Martin Povišer	c6566b660f	memlib.md: Fix typo	2023-09-04 17:38:35 +02:00
Martin Povišer	3de84b959f	memory_libmap: Tweak whitespace	2023-09-04 17:38:35 +02:00
Martin Povišer	50d117956c	sim: Add print support	2023-09-04 17:12:38 +02:00
Miodrag Milanovic	a8809989c4	ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech	2023-08-22 10:50:11 +02:00
Ethan Mahintorabi	d525a41497	abc: Exposes dont_use flag in ABC ABC's read_lib command has a dont_use cell list that is configurable by the user. This PR exposes that option to Yosys. See `5405d4787a/src/map/scl/scl.c (L285)` for documentation on this option. Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>	2023-08-15 20:03:46 +00:00
Charlotte	860e3e4056	proc_clean: only consider fully-defined switch operands too.	2023-08-12 02:46:31 +02:00
Charlotte	bf84861fc2	proc_clean: only consider fully-defined case operands.	2023-08-12 02:46:31 +02:00
whitequark	d51ecde8c2	clean: keep $print cells, since they have unmodelled side effects.	2023-08-11 04:46:52 +02:00
Martin Povišer	ff3c7873f5	wreduce: Group reconnections Group the reconnections, so that instead of producing connect $auto$wreduce.cc:455:run$24 [0] 1'0 connect $auto$wreduce.cc:455:run$23 [31] 1'0 connect $auto$wreduce.cc:455:run$23 [30] 1'0 ... (40 more lines) we produce connect $auto$wreduce.cc:461:run$23 [31:11] 21'000000000000000000000 connect $auto$wreduce.cc:461:run$24 [31:10] 22'0000000000000000000000 .	2023-08-04 14:43:59 +01:00
Martin Povišer	f8325f66b7	opt_expr: Fix 'signed X>=0' replacement for wide output ports If the `$ge` cell we are replacing has wide output port, the upper bits on the port should be driven to zero. That's not what a `$not` cell with a single-bit input does. Instead opt for a `$logic_not` cell, which does zero-pad its output. Fixes #3867.	2023-08-01 13:50:12 +01:00
N. Engelhardt	43780c9812	Merge pull request #3838 from povik/various-cleanup	2023-07-24 16:24:23 +02:00
Catherine	6965abeefa	abc, abc9_exe: fix build on WASI (and others with `const* stdout`). C does not guarantee that stdout/stderr can be reassigned. Most platforms do make them assignable, however musl and WASI that is based on musl do not. WASI does not have `dup2()`; instead it has its own non-portable version of it that can only assign to previously allocated fds. Update the stream redirection code so that it does the right thing on WASI and other platforms.	2023-07-23 05:13:29 +01:00
Catherine	411b6e98cd	abc, abc9_exe: respect `-q` when built with linked ABC. This is mostly important for YoWASP builds, since those do not have a way to build with external ABC (I prototyped it but for some reason ABC always segfaults when built as an independent Wasm binary...)	2023-07-23 02:03:29 +01:00
Martin Povišer	f5485b59a9	sim: Bail if there are blackboxes in simulation	2023-07-20 21:01:03 +01:00
Martin Povišer	f0ae046c5a	opt_share: Fix input confusion with ANDNOT, ORNOT gates Distinguish between the A, B input ports of `$_ANDNOT_`, `$_ORNOT_` gates when considering those for sharing. Unlike the input ports of the other supported single-bit gates, those are not interchangeable. Fixes #3848.	2023-07-20 20:58:52 +01:00
N. Engelhardt	2be5c0786f	Merge pull request #3826 from nakengelhardt/nak/mem_libmap_print_attr	2023-07-17 16:35:10 +02:00
Martin Povišer	eb083c5d4b	extract_counter: Update help and comments after UP/DOWN support Commit `fec7dc5c` should have added support for up counters so update the help and comments accordingly.	2023-07-10 12:45:03 +02:00
N. Engelhardt	57de249881	memory_libmap: print additional debug messages when no valid mapping is found	2023-07-06 18:54:32 +02:00
N. Engelhardt	14d50a176d	Merge pull request #3676 from nakengelhardt/dfflegalize_scratchpad_minarg	2023-07-03 17:15:21 +02:00
N. Engelhardt	a6be7b4751	memory_libmap: add debug messages for some reasons for rejecting mappings	2023-06-29 14:08:31 +02:00
N. Engelhardt	7542146fc5	memory_libmap: print message about attributes forcing ram kind	2023-06-28 17:48:20 +02:00
Jannis Harder	a07f8ac38a	check: Also check for conflicts with constant drivers	2023-06-23 18:07:28 +02:00
Claire Xen	51e627686a	Merge pull request #3812 from charlottia/iterator-invalidation proc_prune: avoid using invalidated iterator	2023-06-21 14:46:25 +02:00
Charlotte	63e4114233	proc_prune: avoid using invalidated iterator An `std::vector<T>::reverse_iterator` stores the `std::vector<T>::iterator` which points to the (forwards-ordered) following item. Thus while `vec.rbegin()` dereferences to the final item of `vec`, the iterator it wraps (`vec.rbegin().base()`) is equal to `vec.end()`. In the remove case here, we advance `it` (backwards), erasing the item we just advanced past by grabbing its (pre-increment) base forward-iterator and subtracting 1. The iterator maths here is obviously all OK, but the forward-iterator that `it` wraps post-increment actually points to the item we just removed. That iterator was invalidated by the `erase()` call. That this works anyway is (AFAICT) some combination of luck and/or promises that aren't part of the C++ spec, but MSVC's debug iterator support picks this up. `erase()` returns the new iterator that follows the item just erased, which happens to be the exact one we want our reverse-iterator to wrap for the next loop; we get a fresh iterator to the same base, now without the preceding item.	2023-06-21 19:53:08 +10:00
N. Engelhardt	9c7f0e7670	show: truncate very long module names	2023-06-20 12:53:56 +02:00
N. Engelhardt	22c9237716	show: escape angle brackets	2023-06-20 11:17:12 +02:00
N. Engelhardt	7c606bd5a3	Merge pull request #3791 from nakengelhardt/nak/show_attr_wires	2023-06-05 16:18:54 +02:00
N. Engelhardt	6f5d984bdb	Merge pull request #3778 from jix/yw_clk2fflogic	2023-06-05 16:15:04 +02:00
N. Engelhardt	0707b911c7	show: add -viewer none option	2023-06-01 11:00:07 +02:00
N. Engelhardt	4b986c9c65	fix wire color after BUF	2023-05-31 17:38:46 +02:00
N. Engelhardt	26555a998d	show -colorattr: extend colors to arrows when wires have attribute	2023-05-26 17:18:21 +02:00
Eddie Hung	ec8d7b1c68	abc9_ops -prep_hier to unmap entire module	2023-05-25 18:42:08 +01:00
Jannis Harder	e36c71b5b7	Use clk2fflogic attr on cells to track original FF names in witnesses This makes clk2fflogic add an attr to $ff cells that carry the state of the emulated async FF. The $ff output doesn't have any async updates that happened in the current cycle, but the $ff input does, so the $ff input corresponds to the async FF's output in the original design. Hence this patch also makes the following changes to passes besides clk2fflogic (but only for FFs with the clk2fflogic attr set): * opt_clean treats the input as a register name (instead of the output) * rename -witness ensures that the input has a public name * the formal backends (smt2, btor, aiger) will use the input's name for the initial state of the FF in witness files * when sim reads a yw witness that assigns an initial value to the input signal, the state update is redirected to the output This ensures that yosys witness files for clk2fflogic designs have useful and stable public signal names. It also makes it possible to simulate a clk2fflogic witness on the original design (with some limitations when the original design is already using $ff cells). It might seem like setting the output of a clk2fflogic FF to update the input's initial value might not work in general, but it works fine for these reasons: * Witnesses for FFs are only present in the initial cycle, so we do not care about any later cycles. * The logic that clk2fflogic generates loops the output of the genreated FF back to the input, with muxes in between to apply any edge or level sensitive updates. So when there are no active updates in the current gclk cycle, there is a combinational path from the output back to the input. * The logic clk2fflogic generates makes sure that an edge sensitive update cannot be active in the first cycle (i.e. the past initial value is assumed to be whatever it needs to be to avoid an edge). * When a level sensitive update is active in the first gclk cycle, it is actively driving the output for the whole gclk cycle, so ignoring any witness initialization is the correct behavior.	2023-05-25 12:48:02 +02:00
Jannis Harder	7caeb922a0	sim: Run level triggered async updates to fixpoint during initialization	2023-05-25 12:46:16 +02:00
gatecat	52c8c28d2c	Add recover_names pass to recover names post-mapping	2023-05-25 10:55:07 +02:00
Jannis Harder	ad2b04d63a	sim: Fix cosimulation with nested modules having unconnected inputs When assigning values to input ports of nested modules in cosimulation, sim needs to find the actual driver of the signal to perform the assignment. The existing code didn't handle unconnected inputs in that scenario.	2023-05-18 16:50:11 +02:00
Muthiah Annamalai (முத்து அண்ணாமலை)	693c609eec	Merge branch 'YosysHQ:master' into main/issue2525	2023-05-16 21:21:32 -07:00
Muthu Annamalai	665e0f6131	remove new line per maintainer request	2023-05-17 04:20:13 +00:00
Miodrag Milanović	acfdc5cc42	Merge pull request #3755 from RTLWorks/muthu/issue3498 [YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style	2023-05-15 16:34:35 +02:00
Muthiah Annamalai (முத்து அண்ணாமலை)	c855502bd5	Update passes/techmap/libparse.cc Allow Liberty canonical identifier including double quotes in if-body and pass-through for Synopsys-style unquoted identifiers issue#3498 Co-authored-by: Aki <201479+lethalbit@users.noreply.github.com>	2023-05-09 06:40:21 -07:00
Miodrag Milanović	226a224640	Merge pull request #3749 from lethalbit/aki/plugin-stuff Updated the `plugin` command to better handle paths	2023-05-09 08:46:02 +02:00
N. Engelhardt	266036c6f9	Merge pull request #3756 from YosysHQ/krys/sim_writeback	2023-05-08 16:21:24 +02:00
N. Engelhardt	ec56e625f4	Merge pull request #3742 from jix/fix_rename_witness_cell_renames	2023-05-08 16:13:28 +02:00
Krystine Sherwin	5a4e72f57a	Fix sim writeback check for yw_cosim Writeback of simulation state into initial state was only working for `run()` and `run_cosim_fst()`. This change moves the writeback into the `write_output_files()` function so that all simulation modes work with the writeback option.	2023-05-08 13:13:09 +12:00
Muthu Annamalai	17cfc969dd	[YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style function body parsing with unittest	2023-05-06 23:37:47 -07:00
Miodrag Milanović	4251d37f4f	Merge pull request #3610 from YosysHQ/synthprop Synthesizable properties	2023-05-05 11:03:09 +02:00
Muthu Annamalai	81e089cb60	[YOSYS-2525] fix read_liberty newline handling #2525 - newlines can be allowed in function parsing	2023-05-04 22:30:27 -07:00
Aki Van Ness	bb240665b7	plugin: shuffled the `#ifdef WITH_PYTHON`'s around to un-tangle the code and pulled out the check for the `.py` extension so it will complain if you try to load a python extension without python support	2023-05-03 03:35:55 -04:00
Aki Van Ness	572c8df9a8	plugin: Re-vamped how plugin lookup was done to make it more consistent with the rest of yosys, and prevented a case where you could end up with `.so.so` on the end	2023-05-03 02:22:46 -04:00
Jannis Harder	7bff8b63b3	rename: Fix renaming cells in -witness mode This was renaming cells while iterating over them which would always cause an assertion failure. Apparently having to rename cells to make all witness signals public is rarely required, so this slipped through.	2023-04-25 12:39:00 +02:00
Benjamin Barzen	8611429237	ABC9: Cell Port Bug Patch (#3670 ) * ABC9: RAMB36E1 Bug Patch * Add simplified testcase * Also fix xaiger writer for under-width output ports * Remove old testcase * Missing top-level input port * Fix tabs --------- Co-authored-by: Eddie Hung <eddie@fpgeh.com>	2023-04-22 16:24:36 -07:00
N. Engelhardt	57897927ff	stat: pass down quiet arg	2023-02-28 17:12:55 +01:00
Miodrag Milanović	21e87f7986	Merge pull request #3646 from YosysHQ/lofty/fix-3591 muxcover: do not add decode muxes with x inputs	2023-02-27 16:26:57 +01:00
Jannis Harder	1c667fab2b	Merge pull request #3672 from jix/yw-cosim-hierarchy-fixes sim: For yw cosim, drive parent module's signals for input ports	2023-02-15 13:45:00 +01:00
N. Engelhardt	b562b54c14	dfflegalize: allow setting mince and minsrst args from scratchpad	2023-02-15 12:53:46 +01:00
Jannis Harder	ec94703619	Merge pull request #2995 from georgerennie/cover_precond chformal: Add -coverenable option	2023-02-14 17:46:31 +01:00
Jannis Harder	85f611fb23	Merge pull request #3126 from georgerennie/equiv_make_assertions equiv_make: Add -make_assert option	2023-02-14 17:15:55 +01:00
Jannis Harder	b636af9751	chformal: Note about using -coverenable with the Verific frontend	2023-02-14 17:10:43 +01:00
Miodrag Milanovic	550a5b7b6b	Update license	2023-02-13 17:23:26 +01:00
Miodrag Milanovic	713b7d3e26	added support for latched output reset	2023-02-13 17:23:26 +01:00
Miodrag Milanovic	131b557727	Initial implementation of synthesizable assertions	2023-02-13 17:23:26 +01:00
Jannis Harder	1698202ccc	sim: For yw cosim, drive parent module's signals for input ports	2023-02-13 12:26:06 +01:00
Miodrag Milanovic	5f33c0e0b2	Updated changelog	2023-02-08 10:11:47 +01:00
N. Engelhardt	417fadbefd	Merge pull request #3625 from povik/show_cleanup	2023-02-06 16:11:26 +01:00
N. Engelhardt	419f91a2b9	add option to fsm_detect to ignore self-resetting	2023-01-30 16:12:53 +01:00
N. Engelhardt	ecfa7e9fbc	add pmux option to bmuxmap for better fsm detection with verific frontend	2023-01-30 16:12:53 +01:00
Lofty	822c7b0341	muxcover: do not add decode muxes with x inputs	2023-01-26 05:19:45 +00:00
Jannis Harder	afac3f2c76	formalff: Fix crash with _NOT_ gates in -hierarchy mode	2023-01-25 12:55:29 +01:00
Miodrag Milanović	8180cc4325	Merge pull request #3624 from jix/sim_yw Changes to support SBY trace generation with the sim command	2023-01-23 16:55:17 +01:00
Miodrag Milanović	245884a101	Merge pull request #3629 from YosysHQ/micko/clang_fixes Fixes for some of clang scan-build detected issues	2023-01-23 16:24:22 +01:00
gatecat	bfacaddca8	show: Remove left-in debug log_warning Signed-off-by: gatecat <gatecat@ds0.me>	2023-01-23 13:54:07 +01:00
Claire Xenia Wolf	bfc3c20cfb	Improve splitcells pass Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2023-01-18 00:31:29 +01:00
Miodrag Milanovic	6574553189	Fixes for some of clang scan-build detected issues	2023-01-17 12:58:08 +01:00
Martin Povišer	f9e30ee5e0	passes: show: s/pos/bitpos/ for readability Signed-off-by: Martin Povišer <povik@cutebit.org>	2023-01-13 19:57:24 +01:00
Martin Povišer	314b864205	passes: show: Reuse string parts in generation of portboxes Signed-off-by: Martin Povišer <povik@cutebit.org>	2023-01-13 19:57:24 +01:00
Martin Povišer	61abca10a3	passes: show: Touch chunk iteration in gen_portbox Signed-off-by: Martin Povišer <povik@cutebit.org>	2023-01-13 19:57:24 +01:00
Martin Povišer	60318a5cd8	passes: show: Label no_signode flag Label the flag and rearrange the control flow a bit. Signed-off-by: Martin Povišer <povik@cutebit.org>	2023-01-13 19:57:24 +01:00
Martin Povišer	8b1f5fba62	passes: show: Simplify wire bit range logic Signed-off-by: Martin Povišer <povik@cutebit.org>	2023-01-13 19:57:24 +01:00
Martin Povišer	ad149cc42a	passes: show: Factor out 'join_label_pieces' In two places, we are joining label pieces by a '\|' separator. We go about it by putting the separator behind each entry, then removing the trailing separator in a final fixup pass on the built string. For easier reading, replace those occurrences by a new factored-out 'join_label_pieces' function. Signed-off-by: Martin Povišer <povik@cutebit.org>	2023-01-13 19:57:24 +01:00
Martin Povišer	5848790835	passes: show: Label signed_suffix flag To make it easier to follow what's going on. Signed-off-by: Martin Povišer <povik@cutebit.org>	2023-01-13 19:57:24 +01:00
Martin Povišer	13700e12e5	passes: show: s/idx/dot_idx/ for readability Signed-off-by: Martin Povišer <povik@cutebit.org>	2023-01-13 19:57:24 +01:00
Martin Povišer	e3709ce776	passes: show: Fix portbox bit ranges in case of driven signals When the 'show' pass generates portboxes to detail the connection of cell ports to wires, it has special handling of signal chunk repetitions, but those repetitions are not accounted for in the displayed bit range in case of cell outputs. Fix that, and so bring it into consistence with the behavior on cell inputs. So, taking for example the following Verilog snippet, module DRIVER (Q); output [7:0] Q; assign Q = 8'b10101010; endmodule module main; wire w; DRIVER driver(.Q({8{w}})); endmodule make the show pass display '7:0 - 8x 0:0' in the driver-to-w portbox instead of '7:7 - 8x 0:0' which it displayed formerly. Signed-off-by: Martin Povišer <povik@cutebit.org>	2023-01-13 19:57:24 +01:00
Jannis Harder	d6c7aa0e3d	sim/formalff: Clock handling for yw cosim	2023-01-11 18:07:16 +01:00
Jannis Harder	7ddec5093f	sim: Improvements and fixes for yw cosim * Fixed $cover handling * Improved sparse memory handling when writing traces * JSON summary output	2023-01-11 18:07:16 +01:00
Jannis Harder	dda972a148	sim: New -append option for Yosys witness cosim This is needed to support SBY's append option.	2023-01-11 18:07:16 +01:00
Jannis Harder	2dd5652215	sim: Add Yosys witness (.yw) cosimulation	2023-01-11 18:07:16 +01:00
Jannis Harder	f6458bab70	sim: Only check formal cells during gclk simulation updates This is required for compatibility with non-multiclock formal semantics.	2023-01-11 18:07:16 +01:00
Jannis Harder	9c6198a827	sim: Internal API to set $initstate This is not yet added to any of the simulation drivers.	2023-01-11 18:07:16 +01:00
Jannis Harder	44b26d5c6d	sim: Emit used memory addresses as signals to output traces This matches the behavior of smtbmc. This also updates the sim internal memory API to allow masked writes where State::Sa bits (internal don't care - not a valid value for a signal) leave the memory content unchanged.	2023-01-11 18:07:16 +01:00
Jannis Harder	5042600c0d	xprop, setundef: Mark xprop decoding bwmuxes, exclude them from setundef This adds the xprop_decoder attribute to bwmuxes that drive the original unencoded signals. Setundef is changed to ignore the x inputs of these bwmuxes, so that they survive the prep script of SBY's formal flow. This is required to make simulation (via sim) using the prep model show the decoded x signals instead of 0/1 values made up by the solver.	2023-01-11 18:07:16 +01:00
N. Engelhardt	4173daa708	Merge pull request #3605 from gadfort/stat-json-area	2023-01-11 16:41:44 +01:00
Claire Xen	843f329b96	Merge branch 'master' into claire/eqystuff	2023-01-11 16:33:08 +01:00
Jannis Harder	5abaa59080	Merge pull request #3537 from jix/xprop New xprop pass	2023-01-11 16:26:04 +01:00
Miodrag Milanovic	5801152779	Deprecate gcc-4.8	2023-01-11 09:54:19 +01:00
Claire Xenia Wolf	6d56d4ecfc	Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuff	2023-01-11 04:10:12 +01:00
Miodrag Milanovic	e3c0fd8b10	qbfsat support for cvc5, fixes #3608	2023-01-09 16:14:01 +01:00
Peter Gadfort	58cca9592d	stat: ensure area is included in json output Signed-off-by: Peter Gadfort <peter.gadfort@gmail.com>	2022-12-29 21:51:46 -05:00
Claire Xenia Wolf	029b0aac7f	Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuff	2022-12-21 14:50:23 +01:00
Claire Xenia Wolf	1bc832a8e1	Allow non-unique modules without state in sim writeback-mode Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-12-21 10:43:02 +01:00
Claire Xenia Wolf	a9072dc23c	Small bugfix in uniquify pass Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-12-21 10:41:48 +01:00
Jannis Harder	4a0ed35aab	xprop: Improve signal splitting code Avoid splitting output ports twice when combining -split-outputs with -split-public and clean up the corresponding code.	2022-12-12 17:51:01 +01:00
Claire Xenia Wolf	6a6e1d8424	Improvements in "viz" pass Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-12-09 18:28:17 +01:00
Jannis Harder	967529abb1	formalff: Proper error messages on async inputs for the -clk2ff mode	2022-12-09 15:25:40 +01:00
Claire Xenia Wolf	dc14def5f3	Add gold-x handing to miter cross port handling Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-12-08 22:14:16 +01:00
Claire Xenia Wolf	3454bddbe2	Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuff	2022-12-08 20:06:23 +01:00
Jannis Harder	172a8e79f0	xprop: Add -split-public option	2022-12-08 20:00:01 +01:00
Claire Xenia Wolf	068031d2aa	Improvements in "viz" command Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-12-07 16:10:58 +01:00
Claire Xenia Wolf	aeba966475	Improvements in "viz" pass Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-12-07 12:46:49 +01:00
Claire Xenia Wolf	c679b408cb	Various improvements in "viz" command Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-12-06 16:43:01 +01:00
Claire Xenia Wolf	2895a66784	Bugfix in splitcells pass Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-12-06 16:00:48 +01:00
Claire Xenia Wolf	e151e44caa	Improvements in "viz" command Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-12-04 19:32:31 +01:00
Claire Xenia Wolf	c9f4b06cb2	Add "viz" pass for visualizing big-picture data flow in larger designs Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-12-04 11:35:10 +01:00
Claire Xenia Wolf	92fc6cd4a9	Add splitcells pass Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-12-04 01:33:04 +01:00
Jannis Harder	7036a312bf	stat: Fix JSON output for empty designs	2022-12-02 14:36:19 +01:00
Jannis Harder	ed02d52f30	tee: Allow logging command output to a given scratchpad value	2022-12-02 14:36:19 +01:00
Claire Xenia Wolf	956b7f5fd1	Merge branch 'xprop' of github.com:jix/yosys into claire/eqystuff	2022-12-01 11:31:39 +01:00
Claire Xenia Wolf	fbf8bcf38f	Add insbuf -chain mode Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-12-01 10:02:35 +01:00
Jannis Harder	eb0039848b	miter: Add -make_cover option to cover each output pair difference	2022-11-30 19:01:28 +01:00
Jannis Harder	551ca7f97f	formalff: Fix -ff2anyinit assertion error for fine FFs	2022-11-30 19:01:28 +01:00
Jannis Harder	ce708122a5	New xprop pass to encode 3-valued x-propagation using 2-valued logic	2022-11-30 19:01:28 +01:00
Jannis Harder	5ff69a0fe2	sim: Improved global clock handling	2022-11-30 18:50:53 +01:00
Jannis Harder	3ecf85e32c	opt_expr: Optimizations for `$bweqx` and `$bwmux`	2022-11-30 18:50:53 +01:00
Jannis Harder	be752a20dc	Add bwmuxmap pass	2022-11-30 18:50:53 +01:00
Jannis Harder	7203ba7bc1	Add bitwise `$bweqx` and `$bwmux` cells The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`) cells enable compact encoding and decoding of 3-valued logic signals using multiple 2-valued signals.	2022-11-30 18:24:35 +01:00
Jannis Harder	1e67c3a3c2	opt_expr: Fix shift/shiftx optimizations	2022-11-30 18:24:25 +01:00
Jannis Harder	fd56d1f79e	opt_expr: Constant fold mux, pmux, bmux, demux, eqx, nex cells	2022-11-29 19:06:45 +01:00
Jannis Harder	c08242ba41	opt_expr: Optimize bitwise logic ops with one fully const input	2022-11-29 19:06:45 +01:00
Jannis Harder	661fa5ff92	simplemap: Map `$xnor` to `$_XNOR_` cells The previous mapping to `$_XOR_` and `$_NOT_` predates the addition of the `$_XNOR_` cell.	2022-11-29 19:06:45 +01:00
Jannis Harder	ed0e14820e	sat: Add -set-def-formal option to force defined $any* outputs	2022-11-28 14:50:52 +01:00
Miodrag Milanovic	b0be19c126	Support importing verilog configurations using Verific	2022-11-25 13:02:11 +01:00
N. Engelhardt	b64141f48b	mention prerequisites in fsm_detect and fsm help	2022-11-21 16:07:23 +01:00
KrystalDelusion	a14dec79eb	Rst docs conversion (#3496 ) Rst docs conversion	2022-11-15 12:55:22 +01:00
Jannis Harder	9b4fba3870	sim: Run a comb-only update step to set past values during FST cosim The previous approach only initialized past_d and past_ad while for FST cosim we also need to initialize the other past values like past_clk, etc. Also to properly initialize them, we need to run a combinational update step in case any of the wires feeding into the FF are private or otherwise not part of the FST.	2022-11-07 14:09:33 +01:00
Claire Xenia Wolf	a4eb7e41c0	Add extra time at the end of a sat VCD trace Otherwise the final values will not show up in gtkwave waveforms when looking at the generated traces. Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-11-01 17:51:46 +01:00
Claire Xenia Wolf	d04c17fd58	Add miter -cross option	2022-10-24 23:23:33 +02:00
Jannis Harder	c77b7343d0	Consistent $mux undef handling * Change simlib's $mux cell to use the ternary operator as $_MUX_ already does * Stop opt_expr -keepdc from changing S=x to S=0 * Change const eval of $mux and $pmux to match the updated simlib (fixes sim) * The sat behavior of $mux already matches the updated simlib The verilog frontend uses $mux for the ternary operators and this changes all interpreations of the $mux cell (that I found) to match the verilog simulation behavior for the ternary operator. For 'if' and 'case' expressions the frontend may also use $mux but uses $eqx if the verilog simulation behavior is requested with the '-ifx' option. For $pmux there is a remaining mismatch between the sat behavior and the simlib behavior. Resolving this requires more discussion, as the $pmux cell does not directly correspond to a specific verilog construct.	2022-10-24 12:03:01 +02:00
Claire Xenia Wolf	0516307637	Add "check -assert" to equiv_opt Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-10-07 16:04:51 +02:00
Claire Xenia Wolf	afa5e6bb53	Exclude primary inputs from quiv_make rewiring Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-10-07 16:04:51 +02:00
Claire Xenia Wolf	381ce66f58	Revert "Merge pull request #641 from tklam/master" This reverts commit `08be796cb8`, reversing changes made to `38dbb44fa0`. This fixes #2728. PR #641 did not actually "fix" #639. The actual issue in #639 is not equiv_make, but assumptions in equiv_simple that are not true for the test case provided in #639.	2022-10-07 16:04:51 +02:00
Jannis Harder	925f92918a	clk2fflogic: Always correctly handle simultaneously changing signals This is a complete rewrite of the FF replacing code. The previous implementation tried to implement the negative hold time by wrapping async control signals individually with pulse stretching. This did not correctly model the interaction between different simultaneously changing inputs (e.g. a falling ALOAD together with a changing AD would load the changed AD instead of the value AD had when ALOAD was high; a falling CLR could mask a raising SET for one cycle; etc.). The new approach first has the logic for all updates using only sampled values followed by the logic for all updates using only current values. That way, e.g., a falling ALOAD will load the sampled AD value but a still active ALOAD will load the current AD value. The new code also has deterministic behavior for the initial state: no operation is active when that operation would depend on a specific previous signal value. This also means clk2fflogic will no longer generate any additional uninitialized FFs. I also documented the negative hold time behavior in the help message, copying the relevant part from async2sync's help messages.	2022-10-07 16:04:51 +02:00
N. Engelhardt	47e73826e0	mutate: warn if less mutations possible than number requested	2022-10-05 10:59:38 +02:00
Miodrag Milanović	fcd1be1422	Merge pull request #3486 from daglem/fix-flowmap-crash Fix crash in flowmap	2022-09-23 16:22:46 +02:00
Kamyar Mohajerani	69787f1906	remove extra space in formating	2022-09-22 15:46:36 +01:00
Kamyar Mohajerani	bc1e579483	stat: add tech tech-specific utilizations to json - refactor resource util. estimation/calculations for Xilinx and CMOS - don't print log_header if "-json" is set	2022-09-22 15:46:36 +01:00
Dag Lem	c4c68e8d86	Fix crash in flowmap In `2fcc1ee72e`, the following is apparantly added in order to mark any number of undefined LUT inputs: lut_a.append(RTLIL::Const(State::Sx, minlut - input_nodes.size())); However this can only be done if the number of input nodes is less than minlut. This fixes #3317	2022-09-20 14:31:19 +02:00
N. Engelhardt	da614fe13a	Fix tmpdir naming when passing -nocleanup option to abc(9) on systems where base_tmpdir isn't /tmp/	2022-09-13 19:30:40 +02:00
N. Engelhardt	d829d7fe00	Merge pull request #3458 from QuantamHD/abc_faster	2022-08-31 08:58:42 +02:00
Miodrag Milanovic	4bc1e1d1f1	Makes sure to set initial_top when change, fixes #3462	2022-08-26 17:12:56 +02:00
N. Engelhardt	7d35003c16	Merge pull request #3449 from YosysHQ/aki/show_pathrw	2022-08-25 17:06:29 +02:00
Ethan Mahintorabi	114253cd54	Improves ABC command runtime by 10-100x After speaking with the author of ABC he let me know that ifraig is a very old command, and that &get; &fraig -x; &put is over 100x faster than ifraig with improved PPA results. After making the change I confirmed that this is in fact a major speed up. On our internal designs in O(millions) of standard cells we saw multi hour reductions in runtime. Also included is an improvement to the dress command. Using AIG based transformations removes the spec it SATs against. Proving the input blif will make sure that no matter what commands are run the dress command can still do its job. I noticed a regression against some LUT mapping jobs that prompted me to fix this.	2022-08-24 00:35:02 +00:00
KrystalDelusion	9465b2af95	Fitting help messages to 80 character width Uses the regex below to search (using vscode): ^\t\tlog$"(.{10,}(?<!\\n)\|.{81,}\\n)"$; Finds any log messages double indented (which help messages are) and checks if either there are is no newline character at the end, or the number of characters before the newline is more than 80.	2022-08-24 10:40:57 +12:00
Aki Van Ness	1433a63165	yosys: passes: cmds: show: added filename re-writing to `show -lib`	2022-08-22 06:04:54 -04:00
Jannis Harder	f7023d06a2	sim: -hdlname option to preserve flattened hierarchy in sim output	2022-08-16 13:37:30 +02:00
Jannis Harder	4ad13c647e	clk2fflogic: Generate less unused logic when using verific Verific generates a lot of FFs with an unused async load and we cannot always optimize that away before running clk2fflogic, so check for that special case here.	2022-08-16 13:37:30 +02:00
Jannis Harder	65145db7e7	rename: Add -witness mode	2022-08-16 13:37:30 +02:00
Jannis Harder	a2f9ebe43a	memory_map: Add -formal option This maps memories for a global clock based formal verification flow. This implies -keepdc, uses $ff cells for ROMs and sets hdlname attributes.	2022-08-16 13:37:30 +02:00
Jannis Harder	0cdb14df41	setundef: Do not add anyseq / anyconst to unused memory port clocks Instead set those unused clocks to zero.	2022-08-16 13:37:30 +02:00
Jannis Harder	428ad5b9fd	wreduce: Keep more x-bits with -keepdc	2022-08-16 13:37:30 +02:00
Jannis Harder	95db5a9d38	formalff: New -setundef option Find FFs with undefined initialization values for which changing the initialization does not change the observable behavior and initialize them. For -ff2anyinit, this reduces the number of generated $anyinit cells that drive wires with private names.	2022-08-16 13:37:30 +02:00
Jannis Harder	a5e1d3b997	formalff: Set new replaced_by_gclk attribute on removed dff's clks This attribute can be used by formal backends to indicate which clocks were mapped to the global clock. Update the btor and smt2 backend which already handle clock inputs to understand this attribute.	2022-08-16 13:37:30 +02:00
Jannis Harder	c0063288d6	Add the $anyinit cell and the formalff pass These can be used to protect undefined flip-flop initialization values from optimizations that are not sound for formal verification and can help mapping all solver-provided values in witness traces for flows that use different backends simultaneously.	2022-08-16 13:37:30 +02:00
N. Engelhardt	6f439dc59a	Merge pull request #3425 from YosysHQ/lofty/stat-json	2022-08-11 17:00:54 +02:00
Lofty	59facfa98c	stat: add option for machine-readable json output	2022-08-11 13:41:01 +01:00
N. Engelhardt	63fca0dbc2	Merge pull request #3277 from YosysHQ/lofty/rename-scramble_name	2022-08-11 12:06:04 +02:00
Miodrag Milanovic	f4a1906721	support file locations containing spaces	2022-08-08 20:30:50 +02:00
Lofty	a48dcd1d40	rename: add -scramble-name option to randomly rename selections	2022-08-08 16:03:28 +01:00
Marcelina Kościelnicka	f679b756d8	opt_reduce: Fix use-after-free. Fixes #3418.	2022-07-23 17:27:26 +02:00
Jannis Harder	14ba50908b	sim: Fix $anyseq in nested modules	2022-07-22 14:48:30 +02:00
Catherine	502b96fe53	Fix external ABC build after commit `0ca0932b5`.	2022-07-07 08:38:30 +00:00
Jannis Harder	4a1e54bf70	Merge pull request #3395 from jix/opt_dff_keepdc_initival opt_dff: With -keepdc, never turn undef init vals into const drivers	2022-07-01 16:52:32 +02:00
Jannis Harder	876ef59f4f	Merge pull request #3396 from jix/async2sync_const_clocks async2sync: turn FFs with const clks into gclk FFs with feedback	2022-07-01 16:47:31 +02:00
Jannis Harder	0182b26aba	Merge pull request #3391 from programmerjake/simcheck-allow-smtlib2-blackboxes add hierarchy -smtcheck	2022-07-01 14:38:45 +02:00
Jannis Harder	5db542742b	async2sync: turn FFs with const clks into gclk FFs with feedback The formal backends do not support multiple clocks. This includes constant clocks. Constant clocks do appear in what isn't a proper multiclock design, for example when mapping not fully initialized ROMs. As converting FFs with constant clocks to FFs using the global is doable even in a single clock flow, make async2sync do this.	2022-06-30 12:09:04 +02:00
Jannis Harder	a47254bd10	opt_dff: With -keepdc, never turn undef init vals into const drivers	2022-06-29 15:42:39 +02:00
Jannis Harder	a6b440b5c9	memory_map: avoid undriven unused FF inputs for -keepdc	2022-06-28 19:05:35 +02:00
Jannis Harder	d78d807a7f	memory_map: -keepdc option for formal Use it when invoking memory_map -rom-only from write_{smt2,btor}.	2022-06-27 15:47:55 +02:00
George Rennie	fbf5d89587	equiv_make: Add -make_assert option This adds a -make_assert flag to equiv_make. When used, the pass generates $eqx and $assert cells to encode equivalence instead of $equiv.	2022-06-24 00:17:02 +01:00
Jacob Lifshay	c16c028831	add hierarchy -smtcheck like -simcheck, but allow smtlib2_module modules.	2022-06-22 20:53:10 -07:00
George Rennie	5dfad5101d	chformal: Rename -coverprecond to -coverenable	2022-06-18 18:28:12 +01:00
Jannis Harder	e39c422734	chformal: Test -coverprecond and reuse the src attribute	2022-06-18 18:19:26 +01:00
George Rennie	c659bd1878	chformal: Add -coverprecond option This inserts $cover cells to cover the enable signal (precondition) for the selected formal cells.	2022-06-18 18:19:26 +01:00
Marcelina Kościelnicka	ab3a9325c3	memory_map: Add -rom-only option.	2022-06-17 16:56:11 +02:00
Marcelina Kościelnicka	01daa077a2	memory_map: Use const drivers instead of FFs for ROMs.	2022-06-17 15:17:14 +02:00
Marcelina Kościelnicka	d69091806a	memory_libmap: Fix wrprio handling.	2022-06-17 02:09:37 +02:00
Marcelina Kościelnicka	25a4cd7020	memory_libmap: Fix params emitted for unused ports for consistency.	2022-06-16 08:14:08 +02:00
N. Engelhardt	3eaa9e38e0	Merge pull request #3196 from bfg86/bfg86/rename Add -suffix option to rename -wire	2022-06-13 16:00:04 +02:00
Marcelina Kościelnicka	1ff0e1a58a	opt_ffinv: Fix use after free.	2022-06-13 14:04:04 +02:00
bfg86	aedd3b7999	Updating help-text with nakengelhardts suggestion.	2022-06-13 09:35:10 +02:00
N. Engelhardt	b8ede6162b	Merge pull request #3349 from nakengelhardt/select_count_scratchpad Make 'stat' and 'select -count' save counts to scratchpad	2022-06-09 17:15:02 +02:00
N. Engelhardt	871b277d35	Merge pull request #3359 from jix/fmcombine-memid fmcombine: Add _gold/_gate suffix to memids	2022-06-09 17:12:34 +02:00
Henner Zeller	9d41aa8e28	Avoid unnecessary copy of a potential large constant value. The local variable is used just to iterate through the values, so a const reference is all we need.	2022-06-09 16:05:51 +01:00
Marcelina Kościelnicka	47efc04a7d	wreduce: Introduce -mux_undef option (aligned with opt_expr).	2022-06-08 21:28:58 +02:00
Lofty	aae2c01326	sta: warn on unrecognised cells only once	2022-06-08 09:31:49 +01:00
Marcelina Kościelnicka	d07828b409	opt_ffinv: Harden against simple ff/inv loop.	2022-06-07 08:20:06 +02:00
Marcelina Kościelnicka	9e8a2ac051	iopadmap: Fix z assignment removal. Fixes #3360.	2022-06-07 04:10:50 +02:00
Jannis Harder	459941c8ff	fmcombine: Add _gold/_gate suffix to memids	2022-06-03 21:52:28 +02:00
Miodrag Milanovic	d88a5d26b7	Fix preventing show crashing with newer graphviz	2022-06-03 08:38:16 +02:00
Marcelina Kościelnicka	71dfbf33b2	Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.	2022-06-02 23:16:12 +02:00
Marcelina Kościelnicka	3a0aa9c663	memory_dff: Add support for no_rw_check attribute.	2022-06-02 12:49:34 +02:00
N. Engelhardt	61b05051e1	also make 'stat' save counts to scratchpad	2022-06-01 16:01:07 +02:00
N. Engelhardt	a55c3db384	have 'select -count' save the count to scratchpad entry 'select.count'	2022-06-01 14:39:33 +02:00
Mohamed A. Bamakhrama	1822be8792	Observe $TMPDIR variable when creating tmp files POSIX defines $TMPDIR as containing the pathname of the directory where programs can create temporary files. On most systems, this variable points to "/tmp". However, on some systems it can point to a different location. Without respecting this variable, yosys fails to run on such systems. Signed-off-by: Mohamed A. Bamakhrama <mohamed@alumni.tum.de>	2022-05-27 15:06:53 +02:00
gatecat	166a175983	abc9_ops: Don't leave unused derived modules lying around These later become accidentally used for techmap replacements for blackboxes that we don't actually want. Signed-off-by: gatecat <gatecat@ds0.me>	2022-05-23 15:02:25 +01:00
Jannis Harder	fc65ea47df	select: Fix -assert-none and -assert-any error output and docs Both of these options consider a selection containing only empty modules as non-empty. This wasn't mentioned in the documentation nor did the error message when using `select -assert-none` list those empty modules, which produced a very confusing error message complaining about a non-empty selection followed by an empty listing of the selection. This fixes the documentation and changes the `-assert-none` and `-assert-any` assertion error messages to also output fully selected modules (this includes selected empty modules). It doesn't change the messages for `-assert-count` etc. as they don't count modules.	2022-05-19 14:07:34 +02:00
Marcelina Kościelnicka	606f1637ae	Add memory_bmux2rom pass.	2022-05-18 22:48:55 +02:00
Marcelina Kościelnicka	7c5dba8b77	Add memory_libmap pass.	2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka	9450f308f0	proc_rom: Add special handling of const-0 address bits.	2022-05-18 17:32:30 +02:00
Marcelina Kościelnicka	98c7804b89	opt_ffinv: Use ModIndex instead of ModWalker. This avoids using out-of-data index information.	2022-05-17 02:52:21 +02:00
Marcelina Kościelnicka	2858bb03cd	Add opt_ffinv pass.	2022-05-13 23:02:30 +02:00
Marcelina Kościelnicka	990c9b8e11	Add proc_rom pass.	2022-05-13 00:37:14 +02:00
Miodrag Milanović	58b23954e8	Merge pull request #3299 from YosysHQ/mmicko/sim_memory sim pass: support for memories	2022-05-09 09:28:09 +02:00
Marcelina Kościelnicka	77b1dfd8c3	opt_mem: Remove constant-value bit lanes.	2022-05-07 23:13:16 +02:00
imhcyx	71166eeecf	memory_share: fix wrong argidx in extra_args	2022-05-05 16:58:39 +08:00
Marcelina Kościelnicka	18a48b1337	abc: Use dict/pool instead of std::map/std::set	2022-05-04 22:04:50 +02:00
Miodrag Milanovic	8e02b3ca30	fix crash when no fst input	2022-05-04 11:21:39 +02:00
Miodrag Milanovic	ad48639cdd	Start restoring memory state from VCD/FST	2022-05-04 10:41:04 +02:00
Miodrag Milanovic	3730db4b98	AIM file could have gaps in or between inputs and inits	2022-05-02 11:18:30 +02:00
Jannis Harder	e0e31bfc5c	Merge pull request #3257 from jix/tribuf-formal tribuf: `-formal` option: convert all to logic and detect conflicts	2022-04-25 16:23:06 +02:00
Miodrag Milanovic	bbfdea2f8a	Match $anyseq input if connected to public wire	2022-04-22 17:20:17 +02:00
Miodrag Milanovic	4d80bc24c7	Treat $anyseq as input from FST	2022-04-22 16:23:39 +02:00
Miodrag Milanovic	33f4009bb5	Last sample from input does not represent change	2022-04-22 13:46:11 +02:00
Miodrag Milanovic	83cad82b29	latches are always set to zero	2022-04-22 12:04:05 +02:00
Miodrag Milanovic	c989adcc2d	If not multiclock, output only on clock edges	2022-04-22 12:03:39 +02:00
Miodrag Milanovic	75032a565d	Set init state for all wires from FST and set past	2022-04-22 11:57:39 +02:00
Miodrag Milanovic	8fa2f3b260	Fix multiclock for btor2 witness	2022-04-22 11:53:41 +02:00
Miodrag Milanović	c3a3f68b4d	Merge pull request #3280 from YosysHQ/micko/fix_readaiw Fix reading aiw from other solvers	2022-04-18 09:49:21 +02:00
Marcelina Kościelnicka	25ff83f0b5	memory_share: Fix up mismatched address widths.	2022-04-15 22:01:00 +02:00
Marcelina Kościelnicka	48eea3efcf	opt_dff: Fix behavior on $ff with D == Q.	2022-04-15 22:00:32 +02:00
Miodrag Milanovic	9508bb2330	Fix reading aiw from other solvers	2022-04-15 11:45:16 +02:00
Jannis Harder	bc48500548	tribuf: `-formal` option: convert all to logic and detect conflicts	2022-04-12 12:46:22 +02:00
Miodrag Milanovic	868409361c	Use wrap_async_control_gate if ff is fine	2022-04-08 16:30:29 +02:00
Iris Johnson	ccc6060f52	Makefile: properly conditionalize features requiring compression.	2022-04-07 20:07:44 -05:00
Catherine	8a1d531b25	Merge pull request #3269 from YosysHQ/micko/fix_autotop Reorder steps in -auto-top to fix synth command, fixes #3261	2022-04-07 22:40:35 +00:00
Marcelina Kościelnicka	376d8cb26f	abc: Add support for FFs with reset in -dff	2022-04-07 15:05:02 +02:00
Miodrag Milanovic	977002b1d2	Reorder steps in -auto-top to fix synth command, fixes #3261	2022-04-05 14:02:37 +02:00
Marcelina Kościelnicka	0aec79a0da	show: Fix width labels. See #3266.	2022-04-04 22:48:09 +02:00
Miodrag Milanovic	6020ba67ac	past_ad initial value setting	2022-04-02 19:13:15 +02:00
Miodrag Milanovic	2c96ecc5f7	setInitState can be only one altering values	2022-04-02 19:13:15 +02:00
Miodrag Milanovic	b54aecd80a	Set past_d value for init state	2022-04-02 19:13:15 +02:00
Jannis Harder	8ca9737180	Merge pull request #3264 from jix/invalid_ff_dcinit_merge opt_merge: Add `-keepdc` option required for formal verification	2022-04-02 12:41:28 +02:00
Jannis Harder	ca5b910296	opt_merge: Add `-keepdc` option required for formal verification The `-keepdc` option prevents merging flipflops with dont-care bits in their initial value, as, in general, this is not a valid transform for formal verification. The keepdc option of `opt` is passed along to `opt_merge` now.	2022-04-01 21:03:20 +02:00
Miodrag Milanovic	86ce441af6	Set init values for wrapped async control signals	2022-04-01 17:44:00 +02:00
Miodrag Milanovic	c95b9b4ba5	Support memories in aiw and multiclock	2022-03-31 13:10:13 +02:00
Lofty	c1057cb3e0	Merge pull request #3194 from Ravenslofty/abc9-flow3mfs abc9: add flow3mfs script	2022-03-28 15:51:04 +01:00
gatecat	8b64dc1dce	abc9_ops: Also derive blackboxes with timing info Signed-off-by: gatecat <gatecat@ds0.me>	2022-03-24 14:36:07 +00:00
Miodrag Milanovic	322ab1cd54	Proper SigBit forming in sim	2022-03-22 14:43:18 +01:00
Miodrag Milanovic	ff3b0c2c46	Proper SigBit forming in sim	2022-03-22 14:22:32 +01:00
Miodrag Milanovic	55eed8df57	More verbose warnings	2022-03-18 14:47:35 +01:00
Miodrag Milanovic	1f3423cd7d	Recognize registers and set initial state for them in tb	2022-03-16 14:35:39 +01:00
Miodrag Milanovic	e217e3017a	Update sim help message.	2022-03-16 07:55:57 +01:00
Miodrag Milanović	25d6fdfea7	Merge pull request #3232 from YosysHQ/micko/fst2tb Added fst2tb pass for generating testbench	2022-03-14 20:01:55 +01:00
Miodrag Milanovic	f5c20b8286	Added fst2tb pass for generating testbench	2022-03-14 19:06:29 +01:00
Claire Xen	5e2992dae2	Merge pull request #3213 from antonblanchard/abc-typo abc: Fix {I} and {P} substitution	2022-03-14 16:05:23 +01:00
Miodrag Milanović	cbece4af0c	Merge pull request #3229 from YosysHQ/micko/sim_date Add date parameter to enable full date/time and version info	2022-03-11 19:02:57 +01:00
Claire Xenia Wolf	e21badd4b3	Add "sim -q" option Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-03-11 16:26:11 +01:00
Miodrag Milanovic	37de369ba7	Add date parameter to enable full date/time and version info	2022-03-11 16:01:59 +01:00
Claire Xenia Wolf	be32de1caa	Small fix in "sim" help message Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-03-11 15:36:23 +01:00
Miodrag Milanovic	5204694123	FstData already do conversion to VCD	2022-03-11 15:21:36 +01:00
Miodrag Milanovic	b72c779204	Support cell name in btor witness file	2022-03-11 15:11:14 +01:00
Miodrag Milanovic	357336339a	Proper write of memory data	2022-03-11 11:19:53 +01:00
Miodrag Milanovic	295b0d1899	Start work on memory init	2022-03-09 18:34:02 +01:00
Miodrag Milanovic	f37ac5d934	Fixes and error check	2022-03-09 09:48:29 +01:00
Miodrag Milanovic	ede348cdc2	cleanup	2022-03-07 16:32:32 +01:00
Miodrag Milanovic	1b1ecd4ab0	Error checks for aiger witness	2022-03-07 15:00:14 +01:00
Miodrag Milanovic	b6aca1d743	btor2 witness co-simulation	2022-03-07 13:59:36 +01:00
Miodrag Milanović	9581b9adac	Merge pull request #3219 from YosysHQ/micko/quick_vcd VCD reader support by using external tool	2022-03-04 10:42:14 +01:00
Miodrag Milanovic	59983eda17	Add option to ignore X only signals in output	2022-03-02 16:02:13 +01:00
Miodrag Milanovic	48b56a4f7f	Write simulation files after simulation is performed	2022-03-02 15:23:07 +01:00
Miodrag Milanovic	28bc88a57e	Cleanup	2022-03-02 09:39:22 +01:00
Miodrag Milanovic	94505395a9	Refactor sim output writers	2022-02-28 18:22:39 +01:00
Miodrag Milanovic	dfd4c81eac	Quick fix	2022-02-28 11:40:06 +01:00
Claire Xenia Wolf	56b968f61c	Add writing of aiw files to "sim" command Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-02-28 10:50:08 +01:00
Claire Xenia Wolf	1fd3a642c9	Hotfix in AIGER witness reader state machine Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-02-28 10:41:44 +01:00
Miodrag Milanovic	8be09b5b24	VCD reader support by using external tool	2022-02-28 09:09:07 +01:00
Miodrag Milanovic	9571acc0bf	Support extended aiw format	2022-02-27 16:37:40 +01:00
Miodrag Milanovic	fca168797e	Fix for last clock edge data	2022-02-25 16:15:32 +01:00
Claire Xenia Wolf	ca261d3c28	Experimental sim changes	2022-02-25 16:02:06 +01:00
Anton Blanchard	89300b2dca	abc: Fix {I} and {P} substitution We were searching for {D} after the first match of {I} or {P}.	2022-02-23 18:54:28 +11:00
Claire Xen	a41c1df76f	Merge pull request #3211 from YosysHQ/micko/witness Add support for AIGER witness files in "sim" command	2022-02-22 16:22:06 +01:00
Miodrag Milanovic	fd3f08753a	Fix handling of ce_over_srst	2022-02-21 16:36:12 +01:00
Claire Xenia Wolf	1aa9ad25d0	Fix cycle 0 in aiger witness co-simulation Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-02-18 16:27:41 +01:00
Miodrag Milanovic	41754b4207	Added AIGER witness file co simulation	2022-02-18 15:04:02 +01:00
Miodrag Milanovic	13a5c28459	simplify logic of handling flip-flops and latches	2022-02-18 09:17:36 +01:00
Miodrag Milanovic	61752b255f	Review cleanup	2022-02-17 17:18:36 +01:00
Miodrag Milanovic	fb22d7cdc4	Add support for various ff/latch cells simulation	2022-02-16 13:27:59 +01:00
Claire Xen	49545c73f7	Merge branch 'master' into clk2ff-better-names	2022-02-11 16:03:12 +01:00
Claire Xen	e016518866	Merge pull request #2019 from boqwxp/glift Add `glift` command for creating gate-level information flow tracking models and optimization problems	2022-02-11 15:51:24 +01:00
bfg86	7ac98d1c87	Add -suffix option to rename -wire. See #3195	2022-02-11 00:05:13 +01:00
Lofty	5ac32ea68c	abc9: add flow3mfs script	2022-02-10 18:28:35 +00:00
Miodrag Milanović	d7f7227ce8	Merge pull request #3185 from YosysHQ/micko/co_sim Add co-simulation in sim pass	2022-02-07 16:36:43 +01:00
Miodrag Milanovic	c0a156bcb4	Error detection for co-simulation	2022-02-04 11:11:36 +01:00
Miodrag Milanovic	6db23de7b1	bug fix and cleanups	2022-02-04 10:01:06 +01:00
YRabbit	f5609d52c4	Correct a typo in the manual Signed-off-by: YRabbit <rabbit@yrabbit.cyou>	2022-02-02 21:14:38 +10:00
Miodrag Milanovic	990aee5531	respect hide_internal flag	2022-02-02 10:15:22 +01:00
Miodrag Milanovic	169ffcd2fb	unify cycles counting and cleanup	2022-02-02 10:08:23 +01:00
Miodrag Milanovic	820b2fdd65	added stimulus mode and param check	2022-02-02 09:37:32 +01:00
Scott Thibault	0a6e2bd5d5	Update comment	2022-02-02 03:21:09 +01:00
Scott Thibault	e04ac4e9e9	Fix unextend method for signed constants	2022-02-02 03:21:09 +01:00
Miodrag Milanovic	8ba2000a50	error when no signal found	2022-01-31 17:41:50 +01:00
Miodrag Milanovic	1b5ff92e62	Cleanup	2022-01-31 13:45:28 +01:00
Miodrag Milanovic	eabd0ff115	Compare bits when not all are defined	2022-01-31 13:41:02 +01:00
Miodrag Milanovic	26de52fa09	Cleanup	2022-01-31 12:00:15 +01:00
Miodrag Milanovic	6513300db7	message update	2022-01-31 11:41:52 +01:00
Miodrag Milanovic	543feb75cb	Display simulation time data	2022-01-31 10:52:47 +01:00
Miodrag Milanovic	a6959d30df	Use edges when explicit	2022-01-31 09:38:25 +01:00
Miodrag Milanovic	cbadfa0268	Updating initial state and checks	2022-01-31 09:19:34 +01:00
Miodrag Milanovic	190e44f0da	Fix scope	2022-01-31 08:56:29 +01:00
Marcelina Kościelnicka	07a657fb0c	opt_reduce: Add $bmux and $demux optimization patterns.	2022-01-30 03:37:52 +01:00
Marcelina Kościelnicka	93508d58da	Add $bmux and $demux cells.	2022-01-28 23:34:41 +01:00
Miodrag Milanovic	f04d1398e5	check if stop before start	2022-01-28 19:41:43 +01:00
Miodrag Milanovic	ecbba625c4	set initial state, only flip-flops	2022-01-28 15:59:13 +01:00

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4833 Commits