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408 Commits

Author SHA1 Message Date
Akash Levy e4066b784d Merge remote-tracking branch 'upstream/main' 2025-03-12 19:21:32 -07:00
Akash Levy 1e9adbe4b0 Add warning statements around the getParam issue 2025-03-12 19:16:10 -07:00
Akash Levy e1fc67a693 Improve the naming in instance add functions 2025-03-05 06:37:36 -08:00
Akash Levy 8117ab228e Use set for strpool_attribute to maintain ordering, but keep some backwards compatibility 2025-03-05 03:28:19 -08:00
Akash Levy 3a67468860 Use ordered set for src attrs when flattening 2025-03-04 23:47:48 -08:00
Akash Levy 7d33fd463b Add is_mostly_const to SigSpec 2025-02-13 11:11:33 -08:00
Martin Povišer 1d57a7cf6b macc_v2: Relax and fix cell check 2025-01-27 15:52:49 +01:00
Martin Povišer aabb4ea1df macc_v2: Fix checks and parameter padding 2025-01-27 13:08:19 +01:00
Martin Povišer cb8f855f34 rtlil: Fix macc_v2 cell check 2025-01-24 12:38:03 +01:00
Martin Povišer 61450e8b6e Update codebase for macc_v2 2025-01-24 12:38:03 +01:00
Martin Povišer 5882055899 macc_v2: Add C port 2025-01-24 12:38:03 +01:00
Martin Povišer c5fd96ebb0 macc_v2: Start new cell 2025-01-24 12:38:03 +01:00
Martin Povišer 08394c51a2 rtlil: Add const append helper 2025-01-24 12:38:03 +01:00
Akash Levy 4f41e01edc const modifier for pool of SigBit -> SigSpec conversion causing linkage errors on Mac 2024-12-20 11:56:10 -08:00
Akash Levy 2508d45f0b Use std::hash for RTLIL hashing 2024-12-19 21:54:57 -08:00
Akash Levy 1dcf75d175 Sync 2024-12-19 21:40:30 -08:00
Emil J. Tywoniak 4e29ec1854 hashlib: acc -> eat 2024-12-18 15:09:25 +01:00
Emil J. Tywoniak d071489ab1 hashlib: redo interface for flexibility 2024-12-18 14:49:25 +01:00
Akash Levy 4356eae4c9 Yosys sync 2024-12-04 14:16:55 -08:00
Krystine Sherwin 9925b27432
Goodbye guidelines (except GettingStarted) 
Drop the parts that are being dropped.
Move the things that are being moved.
Also move the verilog stuff out of README and into the docs.
GettingStarted is less cut and dry, so hold off on that one.
 2024-12-05 09:21:12 +13:00
Krystine Sherwin 1de5d98ae2
Reduce comparisons of size_t and int 
`Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`.
For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
 2024-11-29 12:53:29 +13:00
Akash Levy 1a69c51c88
Merge branch 'YosysHQ:main' into main 2024-11-18 16:10:30 -08:00
Martin Povišer e82e5f8b13 rtlil: Adjust internal check for `$mem_v2` cells 
There's a mismatch between what `kernel/mem.cc` emits for memories
with no read ports and what the internal RTLIL check expects.

The point of dispute it whether some of the parameters relating to read
ports have a zero-width value in this case. The `mem.cc` code says no,
the internal checker says yes.

Surveying the other `$mem_v2` parameters, and internal cell parameters
in general, I am inclined to side with the `mem.cc` code.

This breaks RTLIL compatibility but for an obscure edge case.
 2024-11-08 15:18:43 +01:00
Alain Dargelas 43186b2c7a Returning unsigned int 2024-11-06 16:39:58 -08:00
Alain Dargelas 3ad51e06bc Using Yosys hash 2024-11-06 16:32:18 -08:00
Alain Dargelas 39c2d7aa60 RTLIL Module dump and hash 2024-11-06 15:48:24 -08:00
Akash Levy 7864c6dd34 vector fix for pyosys 2024-10-24 23:12:54 -07:00
Akash Levy 469f5a707a
Merge branch 'YosysHQ:main' into main 2024-10-14 11:21:54 -07:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Akash Levy 8e6ac65dd8
Merge branch 'YosysHQ:main' into main 2024-10-13 10:59:19 -07:00
Philippe Sauter c53c87e1f4 rtlil: add Const:: as_int_compressed function 2024-10-09 19:48:57 +02:00
Philippe Sauter 07fb8af05b rtlil: handle all-zeros case in Const::compress 2024-10-09 19:48:57 +02:00
Philippe Sauter 4cd2e04da4 rtlil: add Const::compress helper function 
Compresses the current bits to the minimum
width representation by removing leading bits.
 2024-10-09 19:48:57 +02:00
Akash Levy 03f740e2a4 Undo annoying commit bdc43c6592 2024-09-18 22:05:23 -07:00
Akash Levy db0317afc5 Add support for int stuff 2024-09-18 16:46:53 -07:00
Martin Povišer 865df26fac Adjust buf-normalized mode 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 80119386c0 Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 4d469f461b Add coarse-grain $buf buffer cell type 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
N. Engelhardt c8b42b7d48
Merge pull request #4538 from RCoeurjoly/verific_bounds 2024-09-12 13:04:04 +02:00
Roland Coeurjoly bdc43c6592 Add left and right bound properties to wire. Add test. Fix printing 
for signed attributes

Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-09-10 12:52:42 +02:00
Jannis Harder f24e2536c6 kernel/rtlil: Add `SigBit operator[](int offset)` to `SigChunk` 
This is already supported by `SigSpec` and since both `SigChunk` and
`SigSpec` implement `extract` which is the multi-bit variant of this,
there is no good reason for `SigChunk` to not support
`SigBit operator[](int offset)`.
 2024-08-21 10:58:39 +01:00
Martin Povišer 89d939334e rtlil: Fix `addShiftx` for signed shifts 
Only the `B` input (the shift amount) can be marked as signed on a
`$shiftx` cell. Adapt the helper accordingly and prevent it from
creating invalid RTLIL when called with `is_signed` set. Previously
it would mark both `A` and `B` as signed.
 2024-06-21 15:14:08 +02:00
Martin Povišer 178eceb32d rtlil: Replace the packed `SigSpec::extract` impl 2024-04-22 16:23:51 +02:00
Jannis Harder 0d30a4d479 rtlil: Add packed `extract` implementation for `SigSpec` 
Previously `extract` on a `SigSpec` would always unpack it. Since a
significant amount of `SigSpec`s have one or few chunks, it's worth
having a dedicated implementation.

This is especially true, since the RTLIL frontend calls into this for
every `wire [lhs:rhs]` slice, making this `extract` take up 40% when
profiling `read_rtlil` with one of the largest coarse grained RTLIL
designs I had on hand.

With this change the `read_rtlil` profile looks like I would expect it
to look like, but I noticed that a lot of the other core RTLIL methods
also are a bit too eager with unpacking or implementing
`SigChunk`/`Const` overloads that just convert to a single chunk
`SigSpec` and forward to the implementation for that, when a direct
implementation would avoid temporary std::vector allocations. While not
relevant for `read_rtlil`, to me it looks like there might be a few easy
overall performance gains to be had by addressing this more generally.
 2024-04-22 13:26:17 +02:00
Jannis Harder f728927307 Add builtin celltype $scopeinfo 
Only declares the cell interface, doesn't make anything use or
understand $scopeinfo yet.
 2024-02-06 17:51:24 +01:00
Catherine c7bf0e3b8f Add new `$check` cell to represent assertions with a message. 2024-02-01 20:10:39 +01:00
N. Engelhardt 027cb31e9d
Merge pull request #4161 from YosysHQ/nak/add_sig_extract_asserts 
SigSpec/SigChunk::extract(): assert offset/length are not out of range
 2024-01-29 16:11:01 +01:00
Martin Povišer c035289383 rtlil: Do not create dummy wires when deleting wires in connections 2024-01-29 11:25:54 +01:00
Martin Povišer d6600fb1d5 rtlil: Fix handling of connections on wire deletion 2024-01-29 11:25:54 +01:00
N. Engelhardt efe4d6dbdc SigSpec/SigChunk::extract(): assert offset/length are not out of range 2024-01-25 12:28:17 +01:00