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19 Commits

Author SHA1 Message Date
Lofty c747466a7a analogdevices: update missed T40LP timings 2026-03-05 05:37:13 +00:00
Lofty 91740645a9 analogdevices: update T40LP timings 2026-03-05 05:37:13 +00:00
Lofty 709746b184 analogdevices: update T16FFC timings 2026-03-05 05:37:13 +00:00
Lofty cd60dd4912 synth_analogdevices: update timing model and tests 2026-03-05 05:37:13 +00:00
Lofty dea8c275ff analogdevices: DSP tweaks 2026-03-05 05:37:12 +00:00
Lofty 39cb61615f analogdevices: DSP inference 2026-03-05 05:37:12 +00:00
Lofty 4954fc980f analogdevices: timings for t40lp 2026-03-05 05:37:12 +00:00
Lofty 2c3876671b analogdevices: use single tech param 2026-03-05 05:37:12 +00:00
Lofty 0a2b6a4f21 analogdevices: expreso does not care about clock buffers 2026-03-05 05:37:12 +00:00
Lofty 6ee0bfa913 analogdevices: prepare for t40lp timings 2026-03-05 05:37:12 +00:00
Krystine Sherwin 9dcffc3dbf analogdevices: Adding RBRAM2 and -tech 2026-03-05 05:37:12 +00:00
Krystine Sherwin 99e26d80b0 analogdevices: (some) Native BRAM 
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
 2026-03-05 05:37:12 +00:00
Krystine Sherwin 376f746bc9 analogdevices: Native LUTRAM primitives 2026-03-05 05:37:12 +00:00
Lofty 30a03886a5 analogdevices: LUTRAM config 2026-03-05 05:37:12 +00:00
Lofty ae5325fe53 analogdevices: update timing model 2026-03-05 05:37:12 +00:00
Lofty c9f6d7b2d4 analogdevices: more housekeeping 2026-03-05 05:37:12 +00:00
Lofty f659cbd159 analogdevices: remove some extra cells! 2026-03-05 05:37:12 +00:00
Lofty 6f205b41f5 test suite 2026-03-05 05:37:12 +00:00
Lofty d5ea7f7016 Create synth_analogdevices 2026-03-05 05:37:12 +00:00