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1444 Commits

Author SHA1 Message Date
Lofty fd05f73d50 dfflibmap: demote some warnings to debug 2024-12-02 14:17:51 +00:00
Emil J. Tywoniak 6b006e5f61 clockgate: reduce build warnings 2024-12-02 10:07:01 +01:00
Martin Povišer 1ded817beb booth: Map simple `$macc` instances too 2024-12-01 16:00:04 +01:00
Martin Povišer 2962f8fa88 techmap: Add `-dont_map` for selective disabling of rules 2024-11-27 15:54:37 +01:00
Alain Dargelas e9b7db0a4a Selective boolopt 2024-11-25 15:22:16 -08:00
Alain Dargelas b2587f5e68 Selective boolopt 2024-11-25 15:19:35 -08:00
Alain Dargelas e8e25b4cea Selective boolopt 2024-11-25 15:18:22 -08:00
Alain Dargelas 10bad88bdb Selective boolopt 2024-11-25 15:15:35 -08:00
Alain Dargelas 13915dee96 Selective boolopt 2024-11-25 15:14:14 -08:00
Alain Dargelas c32d0a412c Selective boolopt 2024-11-25 15:08:42 -08:00
Akash Levy 52a1493548 Naming improvements 2024-11-21 03:29:35 -08:00
Akash Levy f855b39dbb
Merge branch 'YosysHQ:main' into main 2024-11-21 00:34:49 -08:00
Akash Levy b9456acdd1 Remove unused and_cell 2024-11-20 20:36:39 -08:00
Emil J. Tywoniak 4d96cbec75 clockgate: reduce errors to warnings 2024-11-18 18:32:18 +01:00
Emil J. Tywoniak 983c54c75f clockgate: help string add -dont_use and -liberty 2024-11-18 13:57:49 +01:00
Emil J. Tywoniak a5bc36f77e clockgate: add -dont_use 2024-11-18 13:45:30 +01:00
Emil J. Tywoniak e6793da9a0 clockgate: refactor 2024-11-18 12:50:25 +01:00
Akash Levy 0e00fc9824 Add breaksop 2024-11-16 21:58:17 -08:00
Akash Levy aad94abef4 aigmap fix prefix 2024-11-16 21:58:11 -08:00
Akash Levy 6be73e5c2e Updates 2024-11-15 19:02:06 -08:00
Emil J. Tywoniak 45880ea7f2 clockgate: add -liberty 2024-11-14 20:37:59 +01:00
Lofty 4f40187759 dfflibmap: move expression code into libparse 2024-11-13 16:06:57 +00:00
Lofty 08ed2c765e dfflibmap: enable inference 2024-11-13 15:57:45 +00:00
Martin Povišer 9da7341003
Merge pull request #4727 from georgerennie/george/bufnorm_constants2 
bufnorm: preserve constant bits when mapping back to connections
 2024-11-13 14:32:15 +01:00
Akash Levy e99828dc94 Add aigmap 2024-11-12 12:00:09 -08:00
Akash Levy 894c9816d3 Improve naming: big fix 2024-11-11 17:06:11 -08:00
Emil J. Tywoniak 49e1597ea4 filterlib: preserve value quotes 2024-11-12 01:21:07 +01:00
George Rennie ff6c9446c0 bufnorm: preserve constant bits when mapping back to connections 2024-11-12 01:05:15 +01:00
Akash Levy 0e3adb38fc
Merge branch 'YosysHQ:main' into main 2024-11-07 11:24:11 -08:00
George Rennie 8f6058a7d6 bufnorm: preserve constant bits driving wires 2024-11-07 11:48:48 +01:00
Akash Levy c2f95d1b5a Add more Liberty tests and fix parentheses in functions 2024-11-05 10:34:51 -08:00
Akash Levy 72f511ae29 Updates to bmuxmapping and selectconst 2024-11-05 01:00:12 -08:00
Akash Levy 1cba744712 Update 2024-11-04 17:01:41 -08:00
Akash Levy 1eb577120e Bmux unq 2024-11-04 12:03:53 -08:00
Martin Povišer cbe73c9047 cellmatch: Visit whiteboxes for `-derive_luts` 2024-11-04 14:28:46 +01:00
Martin Povišer c9ed6d8dcf cellmatch: Rename `-lut_attrs` to `-derive_luts`; document option 2024-11-04 14:28:40 +01:00
Akash Levy a2ea3c1e7a Fix colon issue 2024-11-01 17:49:29 -07:00
Akash Levy b4d7812662 Add abc, some techmap passes, make opt_balance_tree only balance add/mul 2024-10-30 00:38:05 -07:00
Akash Levy 469f5a707a
Merge branch 'YosysHQ:main' into main 2024-10-14 11:21:54 -07:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Akash Levy bf4b7ec0ea
Merge branch 'YosysHQ:main' into main 2024-10-11 15:40:49 -07:00
Martin Povišer a00137c2f6
Merge pull request #4625 from povik/cellmatch-lut 
cellmatch: Size the `lut` attribute
 2024-10-11 14:08:55 +02:00
Akash Levy fdc4c54c66
Merge branch 'YosysHQ:main' into main 2024-10-07 07:27:27 -10:00
Martin Povišer 9479d3bd3c
Merge pull request #4637 from YosysHQ/emil/bufnorm-warning 
bufnorm: avoid warning. NFC
 2024-10-07 18:01:42 +02:00
Emil J. Tywoniak a76bcdc58f bufnorm: avoid remove warning. NFC 2024-10-07 17:58:48 +02:00
Martin Povišer 2e587c835f abc9_exe: Document SC mapping options 2024-10-07 12:03:49 +02:00
Martin Povišer 3b6dcc7bd0 abc9_exe: Remove `-genlib` option 2024-10-07 12:03:49 +02:00
Martin Povišer e0a86d5483 abc_new: Start new command for aiger2-based round trip 2024-10-07 12:03:49 +02:00
Martin Povišer e58a9b6ab6 abc9: Understand ASIC options similar to `abc` 2024-10-07 12:03:48 +02:00
Akash Levy 654e92e04e Fix Liberty issue 2024-10-03 04:14:20 -07:00
Akash Levy dd487ca8a1 Updating Yosys 2024-10-03 01:46:09 -07:00
Martin Povišer ec42b42bd9 cellmatch: Size the `lut` attribute 2024-10-02 11:29:54 +02:00
Akash Levy 599cebfca5 Include pmuxtree 2024-09-29 05:31:51 -07:00
Akash Levy b1383a80cf Make renaming nicer for bmuxmap -pmux 2024-09-27 00:54:05 -07:00
Akash Levy 9f44ec8aa1
Merge branch 'YosysHQ:main' into main 2024-09-17 15:24:05 -07:00
Martin Povišer 38de01807e Mark `bufnorm` experimental 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 80119386c0 Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 8bb70bac8d Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf d027ead4b5 Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf f4b7ea5fb3 Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 32808a0393 Improvements and fixes to "bufnorm" cmd 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf d0b5dfa6ef Add bufnorm pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Akash Levy 210ec6585f
Merge branch 'YosysHQ:main' into main 2024-09-16 06:59:25 -07:00
Emil J. Tywoniak f193bcf683 clockgate: help string 2024-09-16 14:20:33 +02:00
Emil J. Tywoniak be7c93ec6d clockgate: 1-bit const 0 2024-09-16 13:58:27 +02:00
Emil J a8a92d3469
clockgate: help string 
Co-authored-by: Martin Povišer <povik@cutebit.org>
 2024-09-16 13:55:53 +02:00
Emil J. Tywoniak 1e999a3cb7 clockgate: EN can be a bit on a multi-bit wire 2024-09-11 19:18:25 +02:00
Emil J. Tywoniak 8b464341c2 clockgate: no initvals 2024-09-11 10:24:48 +02:00
Emil J. Tywoniak 7e473299bd clockgate: bail on constant signals 2024-09-09 21:20:19 +02:00
Emil J. Tywoniak e64fceef70 clockgate: prototype clock gating 2024-09-09 15:00:54 +02:00
Akash Levy 4f6a153961 Working tree balance pass 2024-08-27 08:19:17 -07:00
Akash Levy f707a3b6cd
Merge branch 'YosysHQ:main' into main 2024-08-26 22:37:42 -07:00
Krystine Sherwin 7b47f645d7
Address warnings 
- Setting default values
- Fixing mismatched types
- Guarding unused var
 2024-08-16 04:30:31 +12:00
Akash Levy 34e5bc1129
Merge branch 'YosysHQ:main' into master 2024-08-14 16:56:53 -07:00
Martin Povišer 3057c13a66 Improve libparse encapsulation 2024-08-13 18:47:36 +02:00
Martin Povišer 78382eaa6f libparse: Adjust whitespace 2024-08-13 18:47:36 +02:00
Akash Levy aec3df36d1 Make flatten less expressive 2024-07-07 21:46:23 -07:00
Akash Levy 6795c32167 Make scopeinfo not default 2024-06-19 04:05:02 -07:00
Emil J. Tywoniak e939182e68 cellmatch: add comments 2024-05-03 16:42:41 +02:00
Martin Povišer b143e5678f cellmatch: Rename the special design to `$cellmatch` 2024-05-03 16:42:41 +02:00
Martin Povišer c0e68dcc4d cellmatch: Add debug print 2024-05-03 16:42:41 +02:00
Martin Povišer 6a9858cdad cellmatch: Delegate evaluation to `ConstEval` 2024-05-03 16:42:41 +02:00
Martin Povišer 86e1080f05 cellmatch: New pass 2024-05-03 16:42:41 +02:00
Martin Povišer 6ff4ecb2b4 techmap: Remove `techmap_chtype` from the result 2024-05-03 13:33:28 +02:00
Martin Povišer fc82251105 techmap: Support dynamic cell types 2024-05-03 13:33:28 +02:00
Peter Gadfort a48825a604 add support for using ABCs library merging when providing multiple liberty files 2024-04-12 13:57:29 -04:00
N. Engelhardt e4f11eb0a0
Merge pull request #4228 from povik/synth-inject 
synth: Introduce `-extra-map` for amending techmap
 2024-03-11 14:55:45 +01:00
Roland Coeurjoly 4a2fb18718 Changes in libs, passes and tests Makefiles. LDLIBS -> LIBS. LDFLAGS -> LINKFLAGS. CXX is clang++ or g++, not clang and gcc 2024-02-25 17:23:56 +01:00
Roland Coeurjoly 033fa10307 We use CXX instead of LD for linking yosys-filterlib 2024-02-25 16:49:28 +01:00
Martin Povišer 53ca7b48f8 techmap: Fix help message wording 2024-02-22 22:00:56 +01:00
Austin Rovinski 03cadf6474 dfflibmap: use patmatch() from kernel/yosys.cc 
Replace OS matching functions with yosys kernel function

Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
 2024-02-20 11:04:55 -05:00
Austin Rovinski 5059bb1d4f dfflibmap: force PathMatchSpecA on WIN32 
Depending on the WIN32 compilation mode, PathMatchSpec may expect a LPCSTR or
LPCWSTR argument. char* is only convertable to LPCSTR, so use that
implementation

Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
 2024-02-19 14:40:46 -05:00
Austin Rovinski 689feed012 dfflibmap: Add a -dont_use flag to ignore cells 
This is an alternative to setting the dont_use property in lib. This brings
dfflibmap in parity with the abc pass for dont_use.

Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
 2024-02-19 13:00:18 -05:00
Miodrag Milanović edb95c69a9
Merge pull request #4084 from jix/scopeinfo 
$scopeinfo support
 2024-02-12 09:51:22 +01:00
Martin Povišer af1a5cfeb9 Address `SigBit`/`SigSpec` confusion issues under c++20 2024-02-08 17:48:36 +01:00
Jannis Harder 8902fc94b6 Suport $scopeinfo in flatten and opt_clean 2024-02-06 17:51:29 +01:00
Martin Povišer d6566eb344 booth: Redo baseline architecture summation 
Redo the summation logic: strive for some degree of balance on the
generated Wallace tree, emit an `$add` cell for the final summation.
 2023-11-22 15:47:11 +01:00
Martin Povišer beb5cb55a5 booth: Expose `-lowpower` option 2023-11-22 15:29:59 +01:00
Martin Povišer 7005ea9411 booth: Revisit help 2023-11-22 15:29:59 +01:00
Martin Povišer 48b73be8c6 booth: Replace the default signed architecture 
Generalize what was formerly the unsigned-only architecture to support
both signed and unsigned multiplication, use that as default, and set
aside the special low-power architecture that was formerly used for
signed multipliers.
 2023-11-22 15:29:59 +01:00