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1384 Commits

Author SHA1 Message Date
Akash Levy 52a1493548 Naming improvements 2024-11-21 03:29:35 -08:00
Akash Levy f855b39dbb
Merge branch 'YosysHQ:main' into main 2024-11-21 00:34:49 -08:00
Akash Levy b9456acdd1 Remove unused and_cell 2024-11-20 20:36:39 -08:00
Emil J. Tywoniak 4d96cbec75 clockgate: reduce errors to warnings 2024-11-18 18:32:18 +01:00
Emil J. Tywoniak 983c54c75f clockgate: help string add -dont_use and -liberty 2024-11-18 13:57:49 +01:00
Emil J. Tywoniak a5bc36f77e clockgate: add -dont_use 2024-11-18 13:45:30 +01:00
Emil J. Tywoniak e6793da9a0 clockgate: refactor 2024-11-18 12:50:25 +01:00
Akash Levy 0e00fc9824 Add breaksop 2024-11-16 21:58:17 -08:00
Akash Levy aad94abef4 aigmap fix prefix 2024-11-16 21:58:11 -08:00
Akash Levy 6be73e5c2e Updates 2024-11-15 19:02:06 -08:00
Emil J. Tywoniak 45880ea7f2 clockgate: add -liberty 2024-11-14 20:37:59 +01:00
Lofty 4f40187759 dfflibmap: move expression code into libparse 2024-11-13 16:06:57 +00:00
Lofty 08ed2c765e dfflibmap: enable inference 2024-11-13 15:57:45 +00:00
Martin Povišer 9da7341003
Merge pull request #4727 from georgerennie/george/bufnorm_constants2 
bufnorm: preserve constant bits when mapping back to connections
 2024-11-13 14:32:15 +01:00
Akash Levy e99828dc94 Add aigmap 2024-11-12 12:00:09 -08:00
Akash Levy 894c9816d3 Improve naming: big fix 2024-11-11 17:06:11 -08:00
Emil J. Tywoniak 49e1597ea4 filterlib: preserve value quotes 2024-11-12 01:21:07 +01:00
George Rennie ff6c9446c0 bufnorm: preserve constant bits when mapping back to connections 2024-11-12 01:05:15 +01:00
Akash Levy 0e3adb38fc
Merge branch 'YosysHQ:main' into main 2024-11-07 11:24:11 -08:00
George Rennie 8f6058a7d6 bufnorm: preserve constant bits driving wires 2024-11-07 11:48:48 +01:00
Akash Levy c2f95d1b5a Add more Liberty tests and fix parentheses in functions 2024-11-05 10:34:51 -08:00
Akash Levy 72f511ae29 Updates to bmuxmapping and selectconst 2024-11-05 01:00:12 -08:00
Akash Levy 1cba744712 Update 2024-11-04 17:01:41 -08:00
Akash Levy 1eb577120e Bmux unq 2024-11-04 12:03:53 -08:00
Martin Povišer cbe73c9047 cellmatch: Visit whiteboxes for `-derive_luts` 2024-11-04 14:28:46 +01:00
Martin Povišer c9ed6d8dcf cellmatch: Rename `-lut_attrs` to `-derive_luts`; document option 2024-11-04 14:28:40 +01:00
Akash Levy a2ea3c1e7a Fix colon issue 2024-11-01 17:49:29 -07:00
Akash Levy b4d7812662 Add abc, some techmap passes, make opt_balance_tree only balance add/mul 2024-10-30 00:38:05 -07:00
Akash Levy 469f5a707a
Merge branch 'YosysHQ:main' into main 2024-10-14 11:21:54 -07:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Akash Levy bf4b7ec0ea
Merge branch 'YosysHQ:main' into main 2024-10-11 15:40:49 -07:00
Martin Povišer a00137c2f6
Merge pull request #4625 from povik/cellmatch-lut 
cellmatch: Size the `lut` attribute
 2024-10-11 14:08:55 +02:00
Akash Levy fdc4c54c66
Merge branch 'YosysHQ:main' into main 2024-10-07 07:27:27 -10:00
Martin Povišer 9479d3bd3c
Merge pull request #4637 from YosysHQ/emil/bufnorm-warning 
bufnorm: avoid warning. NFC
 2024-10-07 18:01:42 +02:00
Emil J. Tywoniak a76bcdc58f bufnorm: avoid remove warning. NFC 2024-10-07 17:58:48 +02:00
Martin Povišer 2e587c835f abc9_exe: Document SC mapping options 2024-10-07 12:03:49 +02:00
Martin Povišer 3b6dcc7bd0 abc9_exe: Remove `-genlib` option 2024-10-07 12:03:49 +02:00
Martin Povišer e0a86d5483 abc_new: Start new command for aiger2-based round trip 2024-10-07 12:03:49 +02:00
Martin Povišer e58a9b6ab6 abc9: Understand ASIC options similar to `abc` 2024-10-07 12:03:48 +02:00
Akash Levy 654e92e04e Fix Liberty issue 2024-10-03 04:14:20 -07:00
Akash Levy dd487ca8a1 Updating Yosys 2024-10-03 01:46:09 -07:00
Martin Povišer ec42b42bd9 cellmatch: Size the `lut` attribute 2024-10-02 11:29:54 +02:00
Akash Levy 599cebfca5 Include pmuxtree 2024-09-29 05:31:51 -07:00
Akash Levy b1383a80cf Make renaming nicer for bmuxmap -pmux 2024-09-27 00:54:05 -07:00
Akash Levy 9f44ec8aa1
Merge branch 'YosysHQ:main' into main 2024-09-17 15:24:05 -07:00
Martin Povišer 38de01807e Mark `bufnorm` experimental 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 80119386c0 Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 8bb70bac8d Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf d027ead4b5 Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf f4b7ea5fb3 Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00