yosys

Commit Graph

Author	SHA1	Message	Date
Gus Smith	c0f1654028	Expand test into three tests for three cases (1) no check, (2) check with warning, (3) check with error. Previously the single test was not testing all cases, as it was exiting after the first error.	2026-02-23 10:27:36 -08:00
Gus Smith	b454582f54	Detect undriven and error/warn	2026-02-20 11:00:59 -08:00
Jannis Harder	6a0ee6e4fb	Revert sim's cycle_width default back to 10, but keep -width option	2025-10-20 14:40:05 +02:00
Miodrag Milanovic	f11a61b32b	sim: Make cycle width small as possible and configurable	2025-10-16 11:37:44 +02:00
Robert O'Callahan	8b75c06141	Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.	2025-07-22 10:38:38 +00:00
Krystine Sherwin	afd5bbc7fa	fstdata.cc: Fix last step Includes test file for sanity checking simulation steps.	2025-05-12 13:18:19 +12:00
Emil J. Tywoniak	6240aec433	test: restore verific handling, nicer naming	2024-12-13 10:24:47 +01:00
N. Engelhardt	2de9f00368	Merge pull request #4620 from RCoeurjoly/fix-vcd-parsing-ghdl-var-spacing	2024-11-06 16:29:07 +01:00
Roland Coeurjoly	5ea2c6e6e5	Assume x values for missing signal data in FST Co-authored-by: Miodrag Milanovic <mmicko@gmail.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>	2024-10-02 12:08:48 +02:00
Roland Coeurjoly	76c615b2ae	Fix: handle VCD variable references with and without whitespace Co-authored-by: Miodrag Milanović <mmicko@gmail.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>	2024-10-01 11:51:20 +02:00
Lloyd Parkes	49945ab1c2	Replace GNU specific invocation of basename(1) with the equivalent POSIX one. The tests now complete on BSD as well as GNU/Linux.	2022-10-23 11:02:18 +13:00
Miodrag Milanovic	21baf48e04	test dlatchsr and adlatch	2022-02-16 13:58:51 +01:00
Miodrag Milanovic	271ac28b41	Added test cases	2022-02-16 13:27:59 +01:00

13 Commits