luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 01:34:16 +02:00
Code Issues Packages Projects Releases Wiki Activity
16,061 Commits 152 Branches 70 Tags
d0a41d4f58cacc62a30ec27f33763f637512ff21
Commit Graph
1 Commits
Author SHA1 Message Date
Udi Finkelstein 536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
 2018-10-25 02:37:56 +03:00