 Clifford Wolf
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9ac560f5d3
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Add "dffinit -highlow" and fix synth_intel
Signed-off-by: Clifford Wolf <[email protected]>
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2018-01-09 18:42:19 +01:00 |
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 dh73
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3fd1d61e2a
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Initial Cyclone 10 support
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2017-11-08 22:45:21 -06:00 |
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 Larry Doolittle
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50bcd9a728
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Clean whitespace and permissions in techlibs/intel
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2017-10-05 16:23:49 +02:00 |
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Clifford Wolf
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65f91e5120
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Rename "write_verilog -nobasenradix" to "write_verilog -decimal"
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2017-10-03 17:31:21 +02:00 |
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dh73
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4718e65763
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Tested and working altsyncarm without init files
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2017-10-01 19:59:45 -05:00 |
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dh73
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cbaba62401
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Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
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2017-10-01 11:04:17 -05:00 |
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