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148 Commits

Author SHA1 Message Date
Akash Levy 8204fd1d0b Update Yosys to latest 2025-09-06 16:49:39 -07:00
Emil J. Tywoniak 8333a83cef opt_dff: more explicit testing, typo 2025-08-27 11:29:57 +02:00
Anhijkt e1276560cd opt_dff: add another test 2025-08-19 23:48:45 +03:00
Anhijkt e486994f60 opt_dff: add test 2025-08-14 00:13:23 +03:00
Akash Levy cc733fd11b Merge from upstream 2025-07-30 22:50:14 -07:00
Robert O'Callahan 8b75c06141 Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
Akash Levy 3cfbc0d7af
Merge branch 'YosysHQ:main' into main 2025-07-18 09:38:39 -07:00
Martin Povišer 22a44e4333 Start `opt_hier` 2025-07-05 16:45:52 +02:00
Akash Levy 7e9e4c7afe
Merge branch 'YosysHQ:main' into main 2025-06-23 02:30:24 -07:00
George Rennie 7160c91800 tests: add test for #5164 opt_dff -sat UAF 2025-06-06 23:46:23 +01:00
Akash Levy c172eea61f
Merge branch 'YosysHQ:main' into main 2025-05-30 05:00:06 +02:00
George Rennie 353fd0f7f4 tests: test opt_expr for 32 bit unsigned shifts 2025-05-26 15:28:44 +01:00
Akash Levy d520cb42cc
Merge branch 'YosysHQ:main' into main 2025-05-22 10:30:58 -07:00
George Rennie d59380b3a0 tests: more complete testing of shift edgecases 2025-05-08 11:09:01 +02:00
George Rennie af933b4f38 tests: check shifts by amounts that overflow int 2025-05-07 15:12:33 +02:00
Akash Levy 5e0d59ca90
Merge branch 'YosysHQ:main' into main 2025-04-28 18:12:42 -07:00
George Rennie 70a44f035c tests: test opt_expr constant shift edge cases 2025-04-26 12:40:04 +02:00
Akash Levy c0a6985adb
Merge branch 'YosysHQ:main' into main 2025-04-07 14:48:16 -07:00
Krystine Sherwin 406b400458
opt_expr: Fix #4590 
If all the (non-select) inputs of a `$_MUX{4,8,16}_` are undefined, replace it, just like we do for `$mux` and `$_MUX_`.
Add `tests/opt/opt_expr_mux_undef.ys` to verify this.

This doesn't do any const folding on the wide muxes, or shrinking to less wide muxes.  It only handles the case where all inputs are 'x and the mux can be completely removed.
 2025-04-04 12:25:31 +13:00
Akash Levy 439d859bba
Merge branch 'YosysHQ:main' into main 2025-04-03 10:48:42 -07:00
George Rennie 63b3ce0c77
Merge pull request #4971 from Anhijkt/pow-optimization 
opt_expr: optimize pow of 2 cells
 2025-04-03 14:34:36 +02:00
Anhijkt c57cbfa8f9 opt_expr: add test 2025-04-01 21:54:46 +03:00
Akash Levy 027a4cec13
Merge branch 'YosysHQ:main' into main 2025-03-31 14:07:26 -07:00
Emil J 3a1255546a
Merge pull request #4975 from YosysHQ/emil/opt_expr-cover-with-tests 
opt_expr: expand test coverage
 2025-03-31 20:13:16 +02:00
Emil J. Tywoniak 6194eb939d opt_expr: expand test coverage 2025-03-31 19:31:53 +02:00
Akash Levy 3d13f7aae2 Bump to latest 2025-03-26 14:56:10 -07:00
Emil J. Tywoniak 33bfc9d19c opt_merge: test more kinds of cells 2025-03-10 13:14:06 +01:00
Emil J. Tywoniak ae7a97cc2d opt_merge: test some unary cells 2025-03-10 13:14:06 +01:00
Emil J. Tywoniak 176faae7c9 opt_merge: fix trivial binary regression 2025-03-10 13:14:06 +01:00
Akash Levy 33c72b0f25
Merge branch 'YosysHQ:main' into main 2025-02-15 15:54:28 -08:00
Krystine Sherwin db5b76edc1
Add test for shifting by INT_MAX 
Currently resulting in CI failing on main during fsm checks which generate a circuit that simplifies to this.
 2025-02-14 14:01:27 +13:00
Akash Levy ab338b33cb Use equiv_opt -nocells to ensure everything is ok since dffs retain their name 2025-01-16 19:40:18 -08:00
Akash Levy 1dcf75d175 Sync 2024-12-19 21:40:30 -08:00
Emil J. Tywoniak 6240aec433 test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
Akash Levy f855b39dbb
Merge branch 'YosysHQ:main' into main 2024-11-21 00:34:49 -08:00
George Rennie 9043dc0ad6
tests: replace read_ilang with read_rtlil 
* #4612 was written before read_ilang was deprecated but merged after so caused test failures. This switches read_ilang to read_rtlil
 2024-11-20 14:54:23 +01:00
Emil J cc17d5bb70
Merge pull request #4612 from georgerennie/george/opt_demorgan_zero_width 
opt_demorgan: skip zero width cells
 2024-11-20 13:33:16 +01:00
Emil J 18459b4b09
Merge pull request #4614 from georgerennie/george/opt_reduce_cell_width 
opt_reduce: keep at least one input to $reduce_or/and cells
 2024-11-20 13:33:04 +01:00
Akash Levy 1017b19405 Small README updates 2024-11-12 02:53:13 -08:00
Akash Levy fa50434708
Merge branch 'YosysHQ:main' into main 2024-11-08 14:10:24 -08:00
Krystine Sherwin ee73a91f44
Remove references to ilang 2024-11-05 12:36:31 +13:00
George Rennie 0572f8806f opt_reduce: add test for constant $reduce_and/or not being zero width 2024-09-25 16:28:41 +01:00
George Rennie e105cae4a9 opt_demorgan: add test for zero width cell 2024-09-25 16:10:16 +01:00
Akash Levy ed2c65314b Standardize convention, add back test, update README 2024-09-23 06:06:43 -07:00
Akash Levy 79a14e2072 Skip opt_lut test 2024-09-23 05:35:03 -07:00
phsauter 34b5c6d062 peepopt: avoid shift-amount underflow 2024-06-13 23:30:07 +02:00
Martin Povišer 5924d97381 tests: Remove part of test involving combinational loops 2024-03-11 10:45:36 +01:00
Charlotte d130f7fca2 tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
Martin Povišer f8325f66b7 opt_expr: Fix 'signed X>=0' replacement for wide output ports 
If the `$ge` cell we are replacing has wide output port, the upper bits
on the port should be driven to zero. That's not what a `$not` cell with
a single-bit input does. Instead opt for a `$logic_not` cell, which does
zero-pad its output.

Fixes #3867.
 2023-08-01 13:50:12 +01:00
Martin Povišer f0ae046c5a opt_share: Fix input confusion with ANDNOT, ORNOT gates 
Distinguish between the A, B input ports of `$_ANDNOT_`, `$_ORNOT_`
gates when considering those for sharing. Unlike the input ports of the
other supported single-bit gates, those are not interchangeable.

Fixes #3848.
 2023-07-20 20:58:52 +01:00