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16,696 Commits 132 Branches 65 Tags 60 MiB
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19 Commits

Author SHA1 Message Date
Lofty ccbb80dc36 analogdevices: LUT RAM only on positive edge 2026-02-20 10:57:46 +00:00
Lofty 9fdfaf3c79 analogdevices: DSP tweaks 2026-02-20 10:57:46 +00:00
Lofty fa1c859d07 analogdevices: DSP inference 2026-02-20 10:57:46 +00:00
Lofty 9d5ddcb356 analogdevices: remove cells_xtra 2026-02-20 10:57:46 +00:00
Lofty eee01fcf7d analogdevices: timings for t40lp 2026-02-20 10:57:46 +00:00
Lofty 13b4b8c6b9 analogdevices: use single tech param 2026-02-20 10:57:46 +00:00
Lofty f234e553dd analogdevices: expreso does not care about clock buffers 2026-02-20 10:57:46 +00:00
Lofty 1f5e6d5c61 analogdevices: prepare for t40lp timings 2026-02-20 10:57:46 +00:00
Krystine Sherwin 4ba732d1dd analogdevices: Adding RBRAM2 and -tech 2026-02-20 10:57:45 +00:00
Krystine Sherwin 4ff97770f5 analogdevices: (some) Native BRAM 
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
 2026-02-20 10:57:45 +00:00
Krystine Sherwin 49e463bfcc analogdevices: Native LUTRAM primitives 2026-02-20 10:57:45 +00:00
Lofty 5cdda40f14 analogdevices: LUTRAM config 2026-02-20 10:57:45 +00:00
Lofty 3780857f59 analogdevices: update timing model 2026-02-20 10:57:45 +00:00
Lofty d45282042e analogdevices: user retargeting 2026-02-20 10:57:45 +00:00
Lofty 0ee490041e analogdevices: more housekeeping 2026-02-20 10:57:45 +00:00
Lofty 1690678911 analogdevices: remove some extra cells! 2026-02-20 10:57:45 +00:00
Lofty bdf767e65e test suite 2026-02-20 10:57:45 +00:00
Lofty 9055d99215 synth_analogdevices: remove scopeinfo cells 2026-02-20 10:57:45 +00:00
Lofty 80f7d0ee6f Create synth_analogdevices 2026-02-20 10:57:45 +00:00