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5 Commits

Author SHA1 Message Date
Lofty 8fad004fb8 synth_analogdevices: update timing model and tests 2025-11-12 22:44:12 +00:00
Krystine Sherwin d7248303c6 analogdevices: Extra tests 
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
 2025-11-12 22:44:12 +00:00
Lofty e189ee10aa analogdevices: DSP inference 2025-11-12 22:44:12 +00:00
Krystine Sherwin 3cf01c399a analogdevices: Update lutram.ys test 2025-11-12 22:44:12 +00:00
Lofty 8651e3ac89 test suite 2025-11-12 22:44:11 +00:00