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luke/yosys
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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-30 01:48:17 +02:00
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1,761 Commits 148 Branches 70 Tags
c5dbb1aa28f5fb10ebbc0696545ede6fa76ce20b
Commit Graph
6 Commits
Author SHA1 Message Date
Clifford Wolf 4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf e6d33513a5 Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf a7aea17959 Progress in presentation 2014-06-22 12:50:29 +02:00
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