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16200 Commits

Author SHA1 Message Date
Jannis Harder f019e44e74 verificsva: Support the followed-by operator in cover mode 
The implementation for the implication operator in cover mode actually
implements the followed-by operator, so we can re-use it unchanged.

It is not always the correct behavior for the implication operator in
cover mode, but a) it will only cause false positives not miss anything
so if the behavior is unexpected it will be visible in the produced
traces, b) it is unlikely to make a difference for most properties one
would practically use in cover mode, c) at least one other widely used
SVA implementations behaves the same way and d) it's not clear whether
we can fix this without rewriting most of verificsva.cc
 2025-06-13 21:27:31 +02:00
KrystalDelusion 4ade617c41
driver.cc: Don't split options on commas 2025-06-13 10:31:53 +12:00
KrystalDelusion 67f8de54dc
Merge pull request #5160 from garytwong/fast-lex 
verilog: improve string literal matching speed (fixes #5076)
 2025-06-13 09:57:01 +12:00
KrystalDelusion 82888580ac
Merge pull request #5152 from garytwong/unique-if 
verilog: implement SystemVerilog unique/unique0/priority if semantics.
 2025-06-13 09:56:53 +12:00
Emil J c0f52c6ead
Merge pull request #5167 from YosysHQ/emil/fix-splitnets-single-bit-vector 
splitnets: handle single-bit vectors consistently
 2025-06-11 22:47:48 +02:00
Miodrag Milanović e0747b71b7
Merge pull request #5174 from YosysHQ/micko/windows_action 
Update CI, windows-2019 is deprecated
 2025-06-10 08:06:38 +02:00
github-actions[bot] c561ba84e3 Bump version 2025-06-10 00:24:41 +00:00
Miodrag Milanovic a5edbc8836 Update CI, windows-2019 is deprecated 2025-06-09 19:07:53 +02:00
Miodrag Milanovic c16cc539d4 Next dev cycle 2025-06-09 08:12:26 +02:00
Miodrag Milanovic db72ec3bde Release version 0.54 2025-06-09 07:23:54 +02:00
N. Engelhardt 0b19f628e9
Merge pull request #5172 from YosysHQ/nak/reduce_warning_spam 2025-06-08 06:50:56 +00:00
N. Engelhardt cb79e28046
Merge pull request #5159 from YosysHQ/krys/fixing_selections 2025-06-08 06:40:15 +00:00
RonxBulld d079240d38
Allows calling yosys_shutdown and then yosys_setup to restart. 2025-06-07 22:21:09 +08:00
github-actions[bot] 2a25d92413 Bump version 2025-06-07 00:24:11 +00:00
George Rennie 7160c91800 tests: add test for #5164 opt_dff -sat UAF 2025-06-06 23:46:23 +01:00
George Rennie 8c38e2081d opt_dff: don't emit cells until all have been visited to prevent UAF 2025-06-06 23:46:07 +01:00
N. Engelhardt 3fe31294d6 disable warning for intentional use of deprecated function (to assert the feature isn't used any more) 2025-06-06 16:41:25 +02:00
N. Engelhardt f22248f056 downgrade verific warnings about common coding styles 2025-06-06 16:30:50 +02:00
Emil J f123c6f452
Merge pull request #5170 from YosysHQ/emil/revert-log_debug 
Revert log_debug back to macro from function
 2025-06-06 16:29:45 +02:00
N. Engelhardt f1dea78603 don't warn for every blackbox from verific 2025-06-06 15:37:42 +02:00
Emil J. Tywoniak a16227b209 Revert "Change the implementation of log_debug in kernel/log.h from a macro function to a normal function." 
This reverts commit 15cfce061a.
 2025-06-06 15:14:40 +02:00
Emil J. Tywoniak 239c265093 splitnets: handle single-bit vectors consistently 2025-06-05 10:58:06 +02:00
github-actions[bot] 50b63c6481 Bump version 2025-06-05 00:24:30 +00:00
George Rennie 19cdbc5a0c opt_dff: don't remove cells until all have been visited to prevent UAF 2025-06-04 21:02:21 +01:00
Emil J 378add3723
Merge pull request #5163 from YosysHQ/emil/fix-single-bit-vector-leak 
simplify: fix single_bit_vector memory leak
 2025-06-04 17:00:54 +02:00
George Rennie 0fcf5c080d
Merge pull request #5158 from georgerennie/george/task_inout 
read_verilog/astsimplify: copy inout ports in and out of functions/tasks
 2025-06-04 14:23:08 +01:00
George Rennie ab40403d90
Merge pull request #5154 from georgerennie/george/post_incdec_undo_fix 
read_verilog: fix -1 constant used to correct post increment/decrement
 2025-06-04 14:22:32 +01:00
Emil J. Tywoniak c37b7b3bf4 simplify: fix single_bit_vector memory leak 2025-06-04 10:32:03 +02:00
Miodrag Milanovic 784de0f6e3 Make attrmap able to alter memory attributes as well 2025-06-04 08:01:21 +02:00
Emil J c21cd300a0
Merge pull request #5109 from YosysHQ/emil/aiger-map-fix-outputs 
aiger: fix -map and -vmap
 2025-06-02 15:07:19 +02:00
N. Engelhardt 1c742441db
Merge pull request #5150 from YosysHQ/krys/aiger_ordering 2025-06-02 13:06:36 +00:00
Lofty 169f04e634
Merge pull request #5155 from YosysHQ/lofty/codeowners 
CODEOWNERS: add myself for the ABC doc
 2025-06-02 08:38:32 +01:00
Gary Wong ca7d94af99 verilog: improve string literal matching speed (fixes #5076) 
Use a greedy regular expression to match input inside a string
literal, so that flex can accumulate a longer match instead of
invoking a rule for each individual character.
 2025-05-31 22:38:44 -06:00
Gary Wong 10bb0f472f docs: mention related effects for multiplexers in the cell library. 2025-05-30 21:43:33 -06:00
Gary Wong 62660b221f docs: restore and update the note about if/case attributes. 2025-05-30 21:18:09 -06:00
github-actions[bot] 86282027c0 Bump version 2025-05-31 00:23:36 +00:00
George Rennie 97f51bb4b7 tests: add tests for task/function argument input/output copying 2025-05-31 01:21:06 +01:00
Krystine Sherwin 785cabcb0f
abc9_ops: Skip opt_expr in proc 2025-05-31 12:16:37 +12:00
George Rennie 45e8ff476e read_verilog: copy inout ports in and out of functions/tasks 2025-05-31 01:09:03 +01:00
Krystine Sherwin ab0e3cc05f
Proc: Use selections consistently 
All `proc_*` passes now use the same module and process for loops, using `design->all_selected_modules()` and `mod->selected_processes()` respectively.
This simplifies the code, and makes the couple `proc_*` passes that were ignoring boxed modules stop doing that (which seems to have been erroneous rather than intentional).
 2025-05-31 12:04:42 +12:00
KrystalDelusion 545753cc5a
Merge pull request #5143 from YosysHQ/krys/typedef_struct_global 
SystemVerilog: Fix typedef struct in global space
 2025-05-31 09:59:26 +12:00
Krystine Sherwin 6e3922e1c7
functional.cc: Explicit unsorted-pool-as-LIFO 2025-05-31 09:57:43 +12:00
Krystine Sherwin aac562d36a
aiger.cc: Explicit unsorted-pool-as-LIFO 2025-05-31 09:55:00 +12:00
KrystalDelusion 06db8828b2
abc.rst: Clarify larger-but-slower 2025-05-31 09:10:27 +12:00
Lofty e421a03d5a CODEOWNERS: add myself for the ABC doc 2025-05-30 22:05:54 +01:00
George Rennie 3790be114f tests: add tests for verilog pre/post increment/decrement in expressions 2025-05-30 14:38:25 +01:00
George Rennie 70291f0e49 read_verilog: fix -1 constant used to correct post increment/decrement 2025-05-30 14:38:25 +01:00
KrystalDelusion d96d1e3630
Merge pull request #5153 from garytwong/typo-fix 2025-05-30 15:58:59 +12:00
Gary Wong 7a9d727bd0 docs: several small documentation fixes. 2025-05-29 21:26:28 -06:00
Gary Wong 7b09dc31af tests: add cases covering full_case and parallel_case semantics 
This is @KrystalDelusion's suggestion in PR #5141 to verify
sensible implementation of all 4 possible full_case/parallel_case
combinations.

(Also including two similar tests to check the Verilog frontend
applies the correct attributes when given SystemVerilog
priority/unique case and if statements.)
 2025-05-29 20:45:57 -06:00