Commit Graph

112 Commits

Author SHA1 Message Date
Emil J 5278b9cfe1
Merge pull request #5332 from YosysHQ/parse_specify-rebased
Add state_dependent_path_declaration so that `ifnone` can be parsed (rebased)
2025-09-09 21:53:04 +02:00
Robert O'Callahan 9764fa5c41 Remove superfluous/wasteful .c_str()s in log_file_warning() filename parameter 2025-09-09 15:41:03 +02:00
Michael Kupfer 75316e8c49 Add state_dependent_path_declaration so that `ifnone` can be parsed 2025-09-09 13:04:52 +02:00
Emil J. Tywoniak 9a10f4c02f verilog_lexer, verilog_parser: remove comment 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak ae65b4fc84 verilog_lexer: fix fallthrough warning 2025-08-11 13:34:10 +02:00
Emil J 39c5c256c0 verilog_lexer: remove comment
Co-authored-by: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com>
2025-08-11 13:34:10 +02:00
Gary Wong 4ffd05af6f verilog: add support for SystemVerilog string literals.
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-08-11 13:34:10 +02:00
garytwong 105a3cd32d verilog: fix string literal regular expression (#5187)
* verilog: fix string literal regular expression.

A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.

* verilog: add regression test for string literal regex bug.

Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af and fixed by 40aa7eaf).
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak ecec9a760b ast, read_verilog: unify location types, reduce filename copying 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 8bf750ecbb neater errors, lost in the sauce of source 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 4a00169452 ast: ownership for string values 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak c8e0ac0c61 ast, read_verilog: ownership in AST, use C++ styles for parser and lexer 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak f27309136f Revert "verilog: fix string literal regular expression (#5187)"
This reverts commit 834a7294b7.
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 36491569d2 Revert "verilog: add support for SystemVerilog string literals."
This reverts commit 5feb1a1752.
2025-08-11 13:34:10 +02:00
Rahul Bhagwat b776283d79
implement package import 2025-08-03 23:31:54 -04:00
Gary Wong 5feb1a1752 verilog: add support for SystemVerilog string literals.
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-07-03 20:51:12 -06:00
garytwong 834a7294b7
verilog: fix string literal regular expression (#5187)
* verilog: fix string literal regular expression.

A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.

* verilog: add regression test for string literal regex bug.

Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af and fixed by 40aa7eaf).
2025-06-19 12:41:18 -04:00
Gary Wong ca7d94af99 verilog: improve string literal matching speed (fixes #5076)
Use a greedy regular expression to match input inside a string
literal, so that flex can accumulate a longer match instead of
invoking a rule for each individual character.
2025-05-31 22:38:44 -06:00
Charlotte c382d7d3ac fmt: %t/$time support 2023-08-11 04:46:52 +02:00
whitequark 9f8e039a4b ast: use new format string helpers. 2023-08-11 04:46:52 +02:00
Jannis Harder fb1c2be76b verilog: Support void functions
The difference between void functions and tasks is that always_comb's
implicit sensitivity list behaves as if functions were inlined, but
ignores signals read only in tasks. This only matters for event based
simulation, and for synthesis we can treat a void function like a task.
2023-03-20 12:52:46 +01:00
Zachary Snow 15a4e900b2 verilog: support for time scale delay values 2022-02-14 15:58:31 +01:00
Marcelina Kościelnicka 551ef85cd7 verilog: Squash flex-triggered warning. 2021-09-13 18:58:17 +02:00
Marcelina Kościelnicka 52cbf1bea5 verilog: Support tri/triand/trior wire types.
These are, by the standard, just aliases for wire/wand/wor.

Fixes #2918.
2021-08-06 21:35:43 +02:00
Rupert Swarbrick 414154dd27 Add support for parsing the SystemVerilog 'bind' construct
This doesn't do anything useful yet: the patch just adds support for
the syntax to the lexer and parser and adds some tests to check the
syntax parses properly. This generates AST nodes, but doesn't yet
generate RTLIL.

Since our existing hierarchical_identifier parser doesn't allow bit
selects (so you can't do something like foo[1].bar[2].baz), I've also
not added support for a trailing bit select (the "constant_bit_select"
non-terminal in "bind_target_instance" in the spec). If we turn out to
need this in future, we'll want to augment hierarchical_identifier and
its other users too.

Note that you can't easily use the BNF from the spec:

    bind_directive ::=
        "bind" bind_target_scope [ : bind_target_instance_list]
               bind_instantiation ;
      | "bind" bind_target_instance bind_instantiation ;

even if you fix the lookahead problem, because code like this matches
both branches in the BNF:

    bind a b b_i (.*);

The problem is that 'a' could either be a module name or a degenerate
hierarchical reference. This seems to be a genuine syntactic
ambiguity, which the spec resolves (p739) by saying that we have to
wait until resolution time (the hierarchy pass) and take whatever is
defined, treating 'a' as an instance name if it names both an instance
and a module.

To keep the parser simple, it currently accepts this invalid syntax:

    bind a.b : c d e (.*);

This is invalid because we're in the first branch of the BNF above, so
the "a.b" term should match bind_target_scope: a module or interface
identifier, not an arbitrary hierarchical identifier.

This will fail in the hierarchy pass (when it's implemented in a
future patch).
2021-07-16 09:31:39 -04:00
Marcelina Kościelnicka 801ecc0e1d verilog: Squash a memory leak.
That was added in ecc22f7fed
2021-06-14 17:07:41 +02:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
2021-06-08 00:39:36 +02:00
Zachary Snow 15f35d6754 sv: support remaining assignment operators
- Add support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
- Unify existing support for: +=, -=, &=, |=, ^=
2021-05-25 16:15:57 -04:00
Zachary Snow ba2ff1ea98 verilog: revise hot comment warnings 2021-03-30 09:21:18 -04:00
Zachary Snow 0f5b646ab8 sv: extended support for integer types
- Standard data declarations can now use any integer type
- Parameters and localparams can now use any integer type
- Function returns types can now use any integer type
- Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits)
- Added longint type (64 bits)
- Unified parser source for integer type widths
2021-02-28 16:31:56 -05:00
Marcelina Kościelnicka a651204efa Fix handling of unique/unique0/priority cases in the frontend.
Basically:

- priority converts to (* full_case *)
- unique0 converts to (* parallel_case *)
- unique converts to (* parallel_case, full_case *)

Fixes #2596.
2021-02-25 21:53:58 +01:00
clairexen 8ce4f8790e
Merge pull request #2179 from splhack/static-cast
Support SystemVerilog Static Cast
2020-07-01 16:40:20 +02:00
Kamil Rakoczy 539087f417 Support missing sub-assign and and-assign operators
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-25 13:29:06 +02:00
Lukasz Dalek a4b4c22c96 Support missing xor-assign operator
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-24 14:32:12 +02:00
Kamil Rakoczy 22408f24c7 Add plus-assignment operator
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-24 11:54:30 +02:00
Kamil Rakoczy 416a66aee8 Add or-assignment operator
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-24 11:53:50 +02:00
Kazuki Sakamoto 185bbbe681 static cast: support changing size and signedness
Support SystemVerilog Static Cast
- size
- signedness
- (type is not supposted yet)

Fix #535
2020-06-19 17:39:20 -07:00
Peter Crozier 0d3f7ea011
Merge branch 'master' into struct 2020-06-03 17:19:28 +01:00
whitequark 2116d9500c
Merge pull request #2033 from boqwxp/cleanup-verilog-lexer
verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
2020-05-29 06:46:33 +00:00
Rupert Swarbrick 6aa0f72ae9 Silence spurious warning in Verilog lexer when compiling with GCC
The chosen value shouldn't have any effect. I considered something
clearly wrong like -1, but there's no checking inside the generated
lexer, and I suspect this will cause even weirder bugs if triggered
than just setting it to INITIAL.
2020-05-26 17:54:57 +01:00
Peter Crozier f482c9c016 Generalise structs and add support for packed unions. 2020-05-12 14:25:33 +01:00
Peter Crozier 0b6b47ca67 Implement SV structs. 2020-05-08 14:40:49 +01:00
Alberto Gonzalez 323aa1df75
verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace. 2020-05-06 07:22:17 +00:00
Peter Crozier 9a8a644ad1 Error duplicate declarations of a typedef name in the same scope. 2020-03-24 14:35:21 +00:00
Peter Crozier ecc22f7fed Support module/package/interface/block scope for typedef names. 2020-03-23 20:07:22 +00:00
Peter 14f32028ec Parser changes to support typedef. 2020-03-22 18:20:46 -07:00
Marcus Comstedt 5e94bf0291 refixed parsing of constant with comment between size and value
The three parts of a based constant (size, base, digits) are now three
separate tokens, allowing the linear whitespace (including comments)
between them to be treated as normal inter-token whitespace.
2020-03-11 18:21:44 +01:00
Alberto Gonzalez f0afd65035
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes. 2020-02-23 07:22:26 +00:00
Eddie Hung 2e51dc1856 verilog: ignore '&&&' when not in -specify mode 2020-02-13 13:06:13 -08:00
David Shah 4bfd2ef4f3 sv: Improve handling of wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00